ryxiangwei.fit.eqn

数字相位计实现

out_link[6]_reg_input = out_link[6]_or_out;
out_link[6]_p3_out = !Load & !out_link_link[16];
out_link[6] = DFFE(out_link[6]_reg_input, GLOBAL(clk), , , out_link[6]_p3_out);


--C4L21 is lpm_add_sub:i_rtl_1|addcore:adder[0]|p2c[0]~43 at LC23
C4L21_p1_out = C4L2 & out_link[3] & add_num[3];
C4L21_p2_out = C4L2 & C4L3 & add_num[2] & out_link[2];
C4L21_p3_out = C4L2 & C4L3 & C4L4 & add_num[1] & out_link[1];
C4L21_p4_out = C4L2 & C4L3 & C4L4 & C4L5 & add_num[0] & out_link[0];
C4L21_or_out = C4L21_p1_out # C4L21_p2_out # C4L21_p3_out # C4L21_p4_out;
C4L21 = C4L21_or_out;


--add_num[5] is add_num[5] at LC26
add_num[5]_p1_out = Load & !out_link[5];
add_num[5]_p2_out = add_num[5] & Load & add_num[4] & out_link[4];
add_num[5]_p3_out = !add_num[5] & Load & !C4L21 & C4L11;
add_num[5]_p4_out = add_num[5] & Load & C4L21;
add_num[5]_or_out = add_num[5]_p2_out # add_num[5]_p3_out # add_num[5]_p4_out;
add_num[5]_reg_input = add_num[5]_p1_out $ add_num[5]_or_out;
add_num[5] = DFFE(add_num[5]_reg_input, GLOBAL(clk), , , );


--out_link[5] is out_link[5] at LC115
out_link[5]_or_out = out_link_link[5];
out_link[5]_reg_input = out_link[5]_or_out;
out_link[5]_p3_out = !Load & !out_link_link[16];
out_link[5] = DFFE(out_link[5]_reg_input, GLOBAL(clk), , , out_link[5]_p3_out);


--add_num[4] is add_num[4] at LC24
add_num[4]_p1_out = Load & !C4L9 & !add_num[4] & C4L2;
add_num[4]_p2_out = Load & !C4L9 & !out_link[4] & C4L2;
add_num[4]_p3_out = Load & C4L9 & !add_num[4] & !out_link[4];
add_num[4]_p4_out = Load & C4L9 & add_num[4] & out_link[4];
add_num[4]_or_out = add_num[4]_p1_out # add_num[4]_p2_out # add_num[4]_p3_out # add_num[4]_p4_out;
add_num[4]_reg_input = add_num[4]_or_out;
add_num[4] = DFFE(add_num[4]_reg_input, GLOBAL(clk), , , );


--out_link[4] is out_link[4] at LC42
out_link[4]_or_out = out_link_link[4];
out_link[4]_reg_input = out_link[4]_or_out;
out_link[4]_p3_out = !Load & !out_link_link[16];
out_link[4] = DFFE(out_link[4]_reg_input, GLOBAL(clk), , , out_link[4]_p3_out);


--C4L01 is lpm_add_sub:i_rtl_1|addcore:adder[0]|gc[2]~42 at LC21
C4L01_p1_out = add_num[2] & out_link[2];
C4L01_p2_out = C4L4 & add_num[1] & out_link[1];
C4L01_p3_out = C4L4 & C4L5 & add_num[0] & out_link[0];
C4L01_or_out = C4L01_p1_out # C4L01_p2_out # C4L01_p3_out;
C4L01 = C4L01_or_out;


--C4L8 is lpm_add_sub:i_rtl_1|addcore:adder[0]|g3~3 at LC31
C4L8_p1_out = add_num[3] & out_link[3];
C4L8_p2_out = !add_num[3] & !out_link[3];
C4L8_or_out = C4L8_p1_out # C4L8_p2_out;
C4L8 = C4L8_or_out;


--add_num[3] is add_num[3] at LC70
add_num[3]_p1_out = Load & !C4L01 & !C4L8;
add_num[3]_p2_out = Load & C4L01 & C4L8;
add_num[3]_or_out = add_num[3]_p1_out # add_num[3]_p2_out;
add_num[3]_reg_input = add_num[3]_or_out;
add_num[3] = DFFE(add_num[3]_reg_input, GLOBAL(clk), , , );


--out_link[3] is out_link[3] at LC119
out_link[3]_or_out = out_link_link[3];
out_link[3]_reg_input = out_link[3]_or_out;
out_link[3]_p3_out = !Load & !out_link_link[16];
out_link[3] = DFFE(out_link[3]_reg_input, GLOBAL(clk), , , out_link[3]_p3_out);


--C4L71 is lpm_add_sub:i_rtl_1|addcore:adder[0]|unreg_res_node[2]~126 at SEXP29
C4L71 = EXP(add_num[2] & out_link[2]);


--C4L81 is lpm_add_sub:i_rtl_1|addcore:adder[0]|unreg_res_node[2]~128 at LC25
C4L81_p1_out = C4L71 & C4L4;
C4L81_p2_out = add_num[1] & out_link[1];
C4L81_p3_out = add_num[1] & add_num[0] & out_link[0];
C4L81_p4_out = out_link[1] & add_num[0] & out_link[0];
C4L81_or_out = C4L81_p2_out # C4L81_p3_out # C4L81_p4_out;
C4L81 = C4L81_p1_out $ C4L81_or_out;


--add_num[2] is add_num[2] at LC44
add_num[2]_p1_out = Load & C4L81;
add_num[2]_or_out = add_num[2]_p1_out;
add_num[2]_reg_input = add_num[2]_or_out;
add_num[2] = DFFE(add_num[2]_reg_input, GLOBAL(clk), , , );


--out_link[2] is out_link[2] at LC117
out_link[2]_or_out = out_link_link[2];
out_link[2]_reg_input = out_link[2]_or_out;
out_link[2]_p3_out = !Load & !out_link_link[16];
out_link[2] = DFFE(out_link[2]_reg_input, GLOBAL(clk), , , out_link[2]_p3_out);


--A1L65 is i89~8 at SEXP30
A1L65 = EXP(add_num[0] & out_link[0]);


--add_num[1] is add_num[1] at LC30
add_num[1]_p1_out = Load & add_num[0] & out_link[0] & !add_num[1] & !out_link[1];
add_num[1]_p2_out = Load & add_num[0] & out_link[0] & add_num[1] & out_link[1];
add_num[1]_p3_out = Load & add_num[1] & !out_link[1] & A1L65;
add_num[1]_p4_out = Load & !add_num[1] & out_link[1] & A1L65;
add_num[1]_or_out = add_num[1]_p1_out # add_num[1]_p2_out # add_num[1]_p3_out # add_num[1]_p4_out;
add_num[1]_reg_input = add_num[1]_or_out;
add_num[1] = DFFE(add_num[1]_reg_input, GLOBAL(clk), , , );


--out_link[1] is out_link[1] at LC43
out_link[1]_or_out = out_link_link[1];
out_link[1]_reg_input = out_link[1]_or_out;
out_link[1]_p3_out = !Load & !out_link_link[16];
out_link[1] = DFFE(out_link[1]_reg_input, GLOBAL(clk), , , out_link[1]_p3_out);


--add_num[0] is add_num[0] at LC29
add_num[0]_p1_out = Load & add_num[0] & !out_link[0];
add_num[0]_p2_out = Load & !add_num[0] & out_link[0];
add_num[0]_or_out = add_num[0]_p1_out # add_num[0]_p2_out;
add_num[0]_reg_input = add_num[0]_or_out;
add_num[0] = DFFE(add_num[0]_reg_input, GLOBAL(clk), , , );


--out_link[0] is out_link[0] at LC58
out_link[0]_or_out = out_link_link[0];
out_link[0]_reg_input = out_link[0]_or_out;
out_link[0]_p3_out = !Load & !out_link_link[16];
out_link[0] = DFFE(out_link[0]_reg_input, GLOBAL(clk), , , out_link[0]_p3_out);


--out_link_link[14] is out_link_link[14] at LC76
out_link_link[14]_or_out = out_link_link[13];
out_link_link[14]_reg_input = out_link_link[14]_or_out;
out_link_link[14] = DFFE(out_link_link[14]_reg_input, !Txd, , , );


--out_link_link[13] is out_link_link[13] at LC74
out_link_link[13]_or_out = out_link_link[12];
out_link_link[13]_reg_input = out_link_link[13]_or_out;
out_link_link[13] = DFFE(out_link_link[13]_reg_input, !Txd, , , );


--out_link_link[12] is out_link_link[12] at LC71
out_link_link[12]_or_out = out_link_link[11];
out_link_link[12]_reg_input = out_link_link[12]_or_out;
out_link_link[12] = DFFE(out_link_link[12]_reg_input, !Txd, , , );


--out_link_link[11] is out_link_link[11] at LC66
out_link_link[11]_or_out = out_link_link[10];
out_link_link[11]_reg_input = out_link_link[11]_or_out;
out_link_link[11] = DFFE(out_link_link[11]_reg_input, !Txd, , , );


--out_link_link[10] is out_link_link[10] at LC91
out_link_link[10]_or_out = out_link_link[9];
out_link_link[10]_reg_input = out_link_link[10]_or_out;
out_link_link[10] = DFFE(out_link_link[10]_reg_input, !Txd, , , );


--out_link_link[9] is out_link_link[9] at LC90
out_link_link[9]_or_out = out_link_link[8];
out_link_link[9]_reg_input = out_link_link[9]_or_out;
out_link_link[9] = DFFE(out_link_link[9]_reg_input, !Txd, , , );


--out_link_link[8] is out_link_link[8] at LC57
out_link_link[8]_or_out = out_link_link[7];
out_link_link[8]_reg_input = out_link_link[8]_or_out;
out_link_link[8] = DFFE(out_link_link[8]_reg_input, !Txd, , , );


--E2L1 is lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00004~4 at LC6
E2L1_p1_out = add_num[7] & out_link[7];
E2L1_p2_out = add_num[7] & add_num[6] & out_link[6];
E2L1_p3_out = out_link[7] & add_num[6] & out_link[6];
E2L1_p4_out = C4L41 & C4L6;
E2L1_or_out = E2L1_p1_out # E2L1_p2_out # E2L1_p3_out # E2L1_p4_out;
E2L1 = E2L1_or_out;


--C4L9 is lpm_add_sub:i_rtl_1|addcore:adder[0]|g4~8 at LC27
C4L9_p1_out = out_link[3] & add_num[3];
C4L9_p2_out = C4L3 & add_num[2] & out_link[2];
C4L9_p3_out = C4L3 & C4L4 & add_num[1] & out_link[1];
C4L9_p4_out = C4L3 & C4L4 & C4L5 & add_num[0] & out_link[0];
C4L9_or_out = C4L9_p1_out # C4L9_p2_out # C4L9_p3_out # C4L9_p4_out;
C4L9 = C4L9_or_out;


--C2L32 is lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[7]~180 at LC82
C2L32_p1_out = out_link_link1[7] & !add_num[23] & add_num[22] & add_num[21] & add_num[20] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
C2L32 = C2L32_p1_out;


--C2L11 is lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[2]~55 at LC49
C2L11_p1_out = !out_link_link1[2] & !add_num[18];
C2L11_p2_out = add_num[18] & add_num[17] & E2L8 & add_num[16];
C2L11_p3_out = !out_link_link1[2] & !E2L8 & !add_num[16] & C2L6;
C2L11 = C2L11_p1_out # C2L11_p2_out # C2L11_p3_out;


--C4L7 is lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~40 at LC17
C4L7_p1_out = add_num[5] & out_link[5];
C4L7 = C4L7_p1_out;


--E2L9 is lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~397 at LC1
E2L9_p0_out = C5L5 & C5L4 & E2L3 & add_num[10] & out_link[10];
E2L9_p2_out = add_num[13] & out_link[13] & C5L5;
E2L9_p3_out = C5L5 & add_num[11] & C5L4 & out_link[11];
E2L9_p4_out = C5L5 & E2L01 & add_num[12] & out_link[12];
E2L9 = E2L9_p0_out # C5L2 # E2L9_p2_out # E2L9_p3_out # E2L9_p4_out;


--C5L9 is lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[6]~95 at LC3
C5L9_p1_out = add_num[11] & out_link[11];
C5L9_p2_out = E2L3 & add_num[10] & out_link[10];
C5L9 = C5L9_p1_out # C5L9_p2_out;


--A1L45 is i76~18 at LC35
A1L45_p0_out = Load & !out_link[14] & !add_num[14] & E2L2 & C5L8 & C5L6;
A1L45_p1_out = !add_num[13] & Load & !out_link[14] & add_num[14] & !out_link[13];
A1L45_p2_out = !add_num[13] & Load & out_link[14] & !add_num[14] & !out_link[13];
A1L45_p3_out = add_num[13] & Load & !out_link[14] & !add_num[14] & out_link[13];
A1L45_p4_out = add_num[13] & Load & out_link[14] & add_num[14] & out_link[13];
A1L45 = A1L45_p0_out # A1L45_p1_out # A1L45_p2_out # A1L45_p3_out # A1L45_p4_out;


--A1L55 is i77~15 at LC33
A1L55_p1_out = add_num[12] & out_link[12] & add_num[13] & Load;
A1L55_p2_out = !add_num[12] & !out_link[12] & !add_num[13] & Load;
A1L55 = A1L55_p1_out # A1L55_p2_out;


--C4L11 is lpm_add_sub:i_rtl_1|addcore:adder[0]|gn[4]~122sexp at SEXP20
C4L11 = EXP(add_num[4] & out_link[4]);


--C5L6 is lpm_add_sub:i_rtl_1|addcore:adder[1]|ps[4]~63sexp at SEXP33
C5L6 = EXP(!add_num[12] & !out_link[12]);


--C4L51 is lpm_add_sub:i_rtl_1|addcore:adder[0]|ps[6]~57sexp at SEXP17
C4L51 = EXP(!add_num[6] & !out_link[6]);


--C2L2 is lpm_add_sub:i_rtl_0|addcore:adder[0]|g3~6sexp1bal at LC54
C2L2_p1_out = out_link_link1[3] & !add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
C2L2_p2_out = !out_link_link1[3] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
C2L2_p3_out = out_link_link1[3] & add_num[19] & C2L1;
C2L2_p4_out = !out_link_link1[3] & !add_num[19] & C2L1;
C2L2_or_out = C2L2_p1_out # C2L2_p2_out # C2L2_p3_out # C2L2_p4_out;
C2L2 = !(C2L2_or_out);


--C2L91 is lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[7]~119bal at LC108
C2L91_p1_out = out_link_link1[6] & !B1L3;
C2L91_or_out = C2L91_p1_out;
C2L91 = !(C2L91_or_out);


--clk is clk at Pin_83
--operation mode is input

clk = INPUT();


--Load is Load at Pin_29
--operation mode is input

Load = INPUT();


--Txd is Txd at Pin_30
--operation mode is input

Txd = INPUT();


--Rxd is Rxd at Pin_31
--operation mode is input

Rxd = INPUT();


--out_addr[7] is out_addr[7] at Pin_54
--operation mode is output

out_addr[7] = OUTPUT(A1L37Q);


--out_addr[6] is out_addr[6] at Pin_52
--operation mode is output

out_addr[6] = OUTPUT(A1L17Q);


--out_addr[5] is out_addr[5] at Pin_51
--operation mode is output

out_addr[5] = OUTPUT(A1L96Q);


--out_addr[4] is out_addr[4] at Pin_50
--operation mode is output

out_addr[4] = OUTPUT(A1L76Q);


--out_addr[3] is out_addr[3] at Pin_49
--operation mode is output

out_addr[3] = OUTPUT(A1L56Q);


--out_addr[2] is out_addr[2] at Pin_48
--operation mode is output

out_addr[2] = OUTPUT(A1L36Q);


--out_addr[1] is out_addr[1] at Pin_46
--operation mode is output

out_addr[1] = OUTPUT(A1L16Q);


--out_addr[0] is out_addr[0] at Pin_45
--operation mode is output

out_addr[0] = OUTPUT(A1L95Q);


--gate[7] is gate[7] at Pin_69
--operation mode is output

gate[7] = OUTPUT(A1L05Q);


--gate[6] is gate[6] at Pin_68
--operation mode is output

gate[6] = OUTPUT(A1L84Q);


--gate[5] is gate[5] at Pin_67
--operation mode is output

gate[5] = OUTPUT(A1L64Q);


--gate[4] is gate[4] at Pin_65
--operation mode is output

gate[4] = OUTPUT(A1L44Q);


--gate[3] is gate[3] at Pin_64
--operation mode is output

gate[3] = OUTPUT(A1L24Q);


--gate[2] is gate[2] at Pin_63
--operation mode is output

gate[2] = OUTPUT(A1L04Q);


--gate[1] is gate[1] at Pin_61
--operation mode is output

gate[1] = OUTPUT(A1L83Q);


--gate[0] is gate[0] at Pin_60
--operation mode is output

gate[0] = OUTPUT(A1L63Q);






--E2L01 is lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~403 at SEXP3
E2L01 = EXP(!add_num[13] & !out_link[13]);