ryxiangwei.fit.eqn

数字相位计实现

--C2L81 is lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[7]~118 at SEXP81
C2L81 = EXP(add_num[22] & add_num[21] & add_num[20] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16]);


--C2L02 is lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[7]~120 at SEXP82
C2L02 = EXP(out_link_link1[5] & !B1L2 & C2L41);


--C2L12 is lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[7]~121 at SEXP84
C2L12 = EXP(out_link_link1[4] & !B1L1 & C2L41 & C2L31);


--C2L22 is lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[7]~122 at SEXP85
C2L22 = EXP(C2L41 & C2L31 & C2L21 & !C2L3);


--A1L37Q is out_addr[7]~reg0 at LC83
A1L37Q_p1_out = C2L91 & C2L02 & C2L12 & C2L22;
A1L37Q_p0_out = !out_link_link1[7] & !add_num[23] & C2L81;
A1L37Q_p2_out = !out_link_link1[7] & add_num[23] & add_num[22] & add_num[21] & add_num[20] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
A1L37Q_p4_out = out_link_link1[7] & add_num[23] & C2L81;
A1L37Q_or_out = C2L32 # A1L37Q_p0_out # A1L37Q_p2_out # A1L37Q_p4_out;
A1L37Q_reg_input = A1L37Q_p1_out $ A1L37Q_or_out;
A1L37Q = DFFE(A1L37Q_reg_input, GLOBAL(clk), , , Load);


--A1L17Q is out_addr[6]~reg0 at LC80
A1L17Q_p1_out = C2L41 & C2L91;
A1L17Q_p0_out = C2L31 & out_link_link1[4] & !B1L1;
A1L17Q_p2_out = C2L21 & !C2L3 & C2L31;
A1L17Q_p4_out = out_link_link1[5] & !B1L2;
A1L17Q_or_out = A1L17Q_p0_out # A1L17Q_p2_out # A1L17Q_p4_out;
A1L17Q_reg_input = A1L17Q_p1_out $ A1L17Q_or_out;
A1L17Q = DFFE(A1L17Q_reg_input, GLOBAL(clk), , , Load);


--C2L71 is lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[5]~138 at SEXP65
C2L71 = EXP(out_link_link1[5] & !B1L2);


--A1L96Q is out_addr[5]~reg0 at LC77
A1L96Q_p1_out = C2L31 & C2L71;
A1L96Q_p2_out = C2L21 & !C2L3;
A1L96Q_p4_out = out_link_link1[4] & !B1L1;
A1L96Q_or_out = A1L96Q_p2_out # A1L96Q_p4_out;
A1L96Q_reg_input = A1L96Q_p1_out $ A1L96Q_or_out;
A1L96Q = DFFE(A1L96Q_reg_input, GLOBAL(clk), , , Load);


--A1L76Q is out_addr[4]~reg0 at LC75
A1L76Q_p2_out = out_link_link1[4] & !B1L1;
A1L76Q_or_out = A1L76Q_p2_out # !C2L21;
A1L76Q_reg_input = C2L3 $ A1L76Q_or_out;
A1L76Q = DFFE(A1L76Q_reg_input, GLOBAL(clk), , , Load);


--C2L6 is lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[2]~37 at SEXP49
C2L6 = EXP(add_num[17] & out_link_link1[1]);


--C2L7 is lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[2]~38 at SEXP51
C2L7 = EXP(add_num[17] & out_link_link1[0]);


--C2L8 is lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[2]~39 at SEXP52
C2L8 = EXP(E2L8 & add_num[16]);


--C2L9 is lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[2]~40 at SEXP53
C2L9 = EXP(add_num[16] & out_link_link1[0]);


--C2L01 is lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[2]~47 at LC50
C2L01_p0_out = C2L6 & !add_num[18] & C2L9 & !E2L8;
C2L01_p1_out = C2L7 & !out_link_link1[2] & !out_link_link1[1];
C2L01_p2_out = !out_link_link1[2] & C2L8 & !add_num[17] & !out_link_link1[0];
C2L01_p3_out = !out_link_link1[0] & C2L6 & !add_num[16] & !add_num[18];
C2L01_p4_out = !out_link_link1[1] & !add_num[17] & !add_num[18];
C2L01_or_out = C2L11 # C2L01_p0_out # C2L01_p1_out # C2L01_p2_out # C2L01_p3_out # C2L01_p4_out;
C2L01 = C2L01_or_out;


--C2L1 is lpm_add_sub:i_rtl_0|addcore:adder[0]|g3~1 at SEXP54
C2L1 = EXP(add_num[18] & add_num[17] & E2L8 & add_num[16]);


--A1L56Q is out_addr[3]~reg0 at LC73
A1L56Q_or_out = C2L2;
A1L56Q_reg_input = !C2L01 $ A1L56Q_or_out;
A1L56Q = DFFE(A1L56Q_reg_input, GLOBAL(clk), , , Load);


--C2L4 is lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[1]~49 at SEXP55
C2L4 = EXP(!out_link_link1[1] & !add_num[17]);


--C2L5 is lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[1]~54 at LC64
C2L5_p1_out = out_link_link1[1] & !add_num[17] & add_num[16] & E2L8;
C2L5_p2_out = out_link_link1[1] & add_num[17] & C2L8;
C2L5_p3_out = !add_num[16] & E2L8 & C2L4 & out_link_link1[0];
C2L5_p4_out = add_num[16] & !E2L8 & C2L4 & out_link_link1[0];
C2L5_or_out = C2L5_p1_out # C2L5_p2_out # C2L5_p3_out # C2L5_p4_out;
C2L5 = C2L5_or_out;


--C2L61 is lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[2]~156 at LC61
C2L61_p0_out = add_num[17] & add_num[18] & E2L8 & add_num[16];
C2L61_p2_out = !add_num[17] & !add_num[18];
C2L61_p3_out = !add_num[18] & !E2L8;
C2L61_p4_out = !add_num[18] & !add_num[16];
C2L61_or_out = C2L61_p0_out # C2L61_p2_out # C2L61_p3_out # C2L61_p4_out;
C2L61 = out_link_link1[2] $ C2L61_or_out;


--A1L36Q is out_addr[2]~reg0 at LC72
A1L36Q_or_out = !C2L61;
A1L36Q_reg_input = C2L5 $ A1L36Q_or_out;
A1L36Q = DFFE(A1L36Q_reg_input, GLOBAL(clk), , , Load);


--C2L51 is lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[1]~168 at LC62
C2L51_p2_out = !E2L8 & add_num[17];
C2L51_p3_out = add_num[17] & !add_num[16];
C2L51_p4_out = E2L8 & !add_num[17] & add_num[16];
C2L51_or_out = C2L51_p2_out # C2L51_p3_out # C2L51_p4_out;
C2L51 = !out_link_link1[1] $ C2L51_or_out;


--A1L16Q is out_addr[1]~reg0 at LC69
A1L16Q_p2_out = out_link_link1[0] & E2L8 & !add_num[16];
A1L16Q_p4_out = out_link_link1[0] & !E2L8 & add_num[16];
A1L16Q_or_out = A1L16Q_p2_out # A1L16Q_p4_out;
A1L16Q_reg_input = !C2L51 $ A1L16Q_or_out;
A1L16Q = DFFE(A1L16Q_reg_input, GLOBAL(clk), , , Load);


--A1L95Q is out_addr[0]~reg0 at LC67
A1L95Q_p2_out = E2L8 & !add_num[16];
A1L95Q_p4_out = !E2L8 & add_num[16];
A1L95Q_or_out = A1L95Q_p2_out # A1L95Q_p4_out;
A1L95Q_reg_input = out_link_link1[0] $ A1L95Q_or_out;
A1L95Q = DFFE(A1L95Q_reg_input, GLOBAL(clk), , , Load);


--A1L05Q is gate[7]~reg0 at LC107
A1L05Q_p1_out = add_num[22] & add_num[21] & add_num[20] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
A1L05Q_or_out = add_num[23];
A1L05Q_reg_input = A1L05Q_p1_out $ A1L05Q_or_out;
A1L05Q = DFFE(A1L05Q_reg_input, GLOBAL(clk), , , Load);


--A1L84Q is gate[6]~reg0 at LC105
A1L84Q_p1_out = add_num[21] & add_num[20] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
A1L84Q_or_out = add_num[22];
A1L84Q_reg_input = A1L84Q_p1_out $ A1L84Q_or_out;
A1L84Q = DFFE(A1L84Q_reg_input, GLOBAL(clk), , , Load);


--A1L64Q is gate[5]~reg0 at LC104
A1L64Q_p1_out = add_num[20] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
A1L64Q_or_out = add_num[21];
A1L64Q_reg_input = A1L64Q_p1_out $ A1L64Q_or_out;
A1L64Q = DFFE(A1L64Q_reg_input, GLOBAL(clk), , , Load);


--A1L44Q is gate[4]~reg0 at LC101
A1L44Q_p1_out = add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
A1L44Q_or_out = add_num[20];
A1L44Q_reg_input = A1L44Q_p1_out $ A1L44Q_or_out;
A1L44Q = DFFE(A1L44Q_reg_input, GLOBAL(clk), , , Load);


--A1L24Q is gate[3]~reg0 at LC99
A1L24Q_p1_out = add_num[18] & add_num[17] & E2L8 & add_num[16];
A1L24Q_or_out = add_num[19];
A1L24Q_reg_input = A1L24Q_p1_out $ A1L24Q_or_out;
A1L24Q = DFFE(A1L24Q_reg_input, GLOBAL(clk), , , Load);


--A1L04Q is gate[2]~reg0 at LC97
A1L04Q_p0_out = !add_num[18] & add_num[17] & E2L8 & add_num[16];
A1L04Q_p1_out = add_num[18] & !add_num[17];
A1L04Q_p2_out = add_num[18] & !E2L8;
A1L04Q_p4_out = add_num[18] & !add_num[16];
A1L04Q_or_out = A1L04Q_p0_out # A1L04Q_p1_out # A1L04Q_p2_out # A1L04Q_p4_out;
A1L04Q_reg_input = A1L04Q_or_out;
A1L04Q = DFFE(A1L04Q_reg_input, GLOBAL(clk), , , Load);


--A1L83Q is gate[1]~reg0 at LC94
A1L83Q_p1_out = add_num[17] & !E2L8;
A1L83Q_p2_out = add_num[17] & !add_num[16];
A1L83Q_p4_out = !add_num[17] & E2L8 & add_num[16];
A1L83Q_or_out = A1L83Q_p1_out # A1L83Q_p2_out # A1L83Q_p4_out;
A1L83Q_reg_input = A1L83Q_or_out;
A1L83Q = DFFE(A1L83Q_reg_input, GLOBAL(clk), , , Load);


--A1L63Q is gate[0]~reg0 at LC93
A1L63Q_p1_out = E2L8 & !add_num[16];
A1L63Q_p2_out = !E2L8 & add_num[16];
A1L63Q_or_out = A1L63Q_p1_out # A1L63Q_p2_out;
A1L63Q_reg_input = A1L63Q_or_out;
A1L63Q = DFFE(A1L63Q_reg_input, GLOBAL(clk), , , Load);


--C2L41 is lpm_add_sub:i_rtl_0|addcore:adder[0]|ps[6]~57 at LC106
C2L41_p2_out = out_link_link1[6] & !add_num[22];
C2L41_p3_out = !out_link_link1[6] & add_num[21] & add_num[20] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
C2L41_or_out = C2L41_p2_out # C2L41_p3_out;
C2L41 = add_num[22] $ C2L41_or_out;


--C2L31 is lpm_add_sub:i_rtl_0|addcore:adder[0]|ps[5]~62 at LC89
C2L31_p2_out = out_link_link1[5] & !add_num[21];
C2L31_p3_out = !out_link_link1[5] & add_num[20] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
C2L31_or_out = C2L31_p2_out # C2L31_p3_out;
C2L31 = add_num[21] $ C2L31_or_out;


--C2L21 is lpm_add_sub:i_rtl_0|addcore:adder[0]|ps[4]~67 at LC88
C2L21_p2_out = out_link_link1[4] & !add_num[20];
C2L21_p3_out = !out_link_link1[4] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
C2L21_or_out = C2L21_p2_out # C2L21_p3_out;
C2L21 = add_num[20] $ C2L21_or_out;


--C2L3 is lpm_add_sub:i_rtl_0|addcore:adder[0]|g4~2 at LC56
C2L3_p1_out = !C2L01 & C2L2;
C2L3_p2_out = add_num[18] & add_num[17] & E2L8 & add_num[16] & add_num[19];
C2L3_p3_out = !add_num[19] & C2L1;
C2L3_or_out = C2L3_p2_out # C2L3_p3_out # !out_link_link1[3];
C2L3 = C2L3_p1_out $ C2L3_or_out;


--out_link_link1[4] is out_link_link1[4] at LC41
out_link_link1[4]_or_out = out_link_link[4];
out_link_link1[4]_reg_input = out_link_link1[4]_or_out;
out_link_link1[4]_p3_out = !Load & out_link_link[16];
out_link_link1[4] = DFFE(out_link_link1[4]_reg_input, GLOBAL(clk), , , out_link_link1[4]_p3_out);


--B1L1 is lpm_add_sub:i_rtl_0|datab_node[4]~49 at LC102
B1L1_p1_out = add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
B1L1_or_out = !add_num[20];
B1L1 = B1L1_p1_out $ B1L1_or_out;


--out_link_link1[1] is out_link_link1[1] at LC45
out_link_link1[1]_or_out = out_link_link[1];
out_link_link1[1]_reg_input = out_link_link1[1]_or_out;
out_link_link1[1]_p3_out = !Load & out_link_link[16];
out_link_link1[1] = DFFE(out_link_link1[1]_reg_input, GLOBAL(clk), , , out_link_link1[1]_p3_out);


--out_link_link1[0] is out_link_link1[0] at LC53
out_link_link1[0]_or_out = out_link_link[0];
out_link_link1[0]_reg_input = out_link_link1[0]_or_out;
out_link_link1[0]_p3_out = !Load & out_link_link[16];
out_link_link1[0] = DFFE(out_link_link1[0]_reg_input, GLOBAL(clk), , , out_link_link1[0]_p3_out);


--add_num[23] is add_num[23] at LC100
add_num[23]_p1_out = Load & add_num[22] & add_num[21] & add_num[20] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
add_num[23]_p2_out = !Load & add_num[23];
add_num[23]_or_out = add_num[23]_p1_out # add_num[23]_p2_out;
add_num[23]_reg_input = add_num[23]_or_out;
add_num[23] = TFFE(add_num[23]_reg_input, GLOBAL(clk), , , );


--add_num[22] is add_num[22] at LC98
add_num[22]_p1_out = Load & add_num[21] & add_num[20] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
add_num[22]_p2_out = !Load & add_num[22];
add_num[22]_or_out = add_num[22]_p1_out # add_num[22]_p2_out;
add_num[22]_reg_input = add_num[22]_or_out;
add_num[22] = TFFE(add_num[22]_reg_input, GLOBAL(clk), , , );


--add_num[21] is add_num[21] at LC110
add_num[21]_p1_out = Load & add_num[20] & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
add_num[21]_p2_out = !Load & add_num[21];
add_num[21]_or_out = add_num[21]_p1_out # add_num[21]_p2_out;
add_num[21]_reg_input = add_num[21]_or_out;
add_num[21] = TFFE(add_num[21]_reg_input, GLOBAL(clk), , , );


--add_num[20] is add_num[20] at LC111
add_num[20]_p1_out = Load & add_num[19] & add_num[18] & add_num[17] & E2L8 & add_num[16];
add_num[20]_p2_out = !Load & add_num[20];
add_num[20]_or_out = add_num[20]_p1_out # add_num[20]_p2_out;
add_num[20]_reg_input = add_num[20]_or_out;
add_num[20] = TFFE(add_num[20]_reg_input, GLOBAL(clk), , , );


--add_num[19] is add_num[19] at LC52
add_num[19]_p1_out = Load & add_num[18] & add_num[17] & E2L8 & add_num[16];
add_num[19]_p2_out = !Load & add_num[19];
add_num[19]_or_out = add_num[19]_p1_out # add_num[19]_p2_out;
add_num[19]_reg_input = add_num[19]_or_out;
add_num[19] = TFFE(add_num[19]_reg_input, GLOBAL(clk), , , );


--add_num[18] is add_num[18] at LC51
add_num[18]_p1_out = Load & add_num[17] & E2L8 & add_num[16];
add_num[18]_p2_out = !Load & add_num[18];
add_num[18]_or_out = add_num[18]_p1_out # add_num[18]_p2_out;
add_num[18]_reg_input = add_num[18]_or_out;
add_num[18] = TFFE(add_num[18]_reg_input, GLOBAL(clk), , , );


--add_num[17] is add_num[17] at LC84
add_num[17]_p1_out = Load & E2L8 & add_num[16];
add_num[17]_p2_out = !Load & add_num[17];
add_num[17]_or_out = add_num[17]_p1_out # add_num[17]_p2_out;
add_num[17]_reg_input = add_num[17]_or_out;
add_num[17] = TFFE(add_num[17]_reg_input, GLOBAL(clk), , , );


--E2L2 is lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~385 at SEXP37
E2L2 = EXP(!add_num[13] & !out_link[13]);


--E2L3 is lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~386 at SEXP5
E2L3 = EXP(!add_num[11] & !out_link[11]);


--E2L4 is lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~387 at SEXP6
E2L4 = EXP(!add_num[10] & !out_link[10]);


--E2L5 is lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~388 at SEXP7
E2L5 = EXP(!add_num[9] & !out_link[9]);


--E2L6 is lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~389 at SEXP8
E2L6 = EXP(!add_num[8] & !out_link[8]);


--E2L7 is lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~390 at SEXP9
E2L7 = EXP(!add_num[7] & !out_link[7]);


--C5L5 is lpm_add_sub:i_rtl_1|addcore:adder[1]|prop_node[3]~100 at LC47
C5L5_p1_out = add_num[15] & add_num[14];
C5L5_p2_out = add_num[15] & out_link[14];
C5L5_p3_out = add_num[14] & out_link[15];
C5L5_p4_out = out_link[14] & out_link[15];
C5L5_or_out = C5L5_p1_out # C5L5_p2_out # C5L5_p3_out # C5L5_p4_out;
C5L5 = C5L5_or_out;


--C5L4 is lpm_add_sub:i_rtl_1|addcore:adder[1]|prop_node[2]~105 at LC8
C5L4_p1_out = add_num[13] & add_num[12];
C5L4_p2_out = add_num[13] & out_link[12];
C5L4_p3_out = add_num[12] & out_link[13];
C5L4_p4_out = out_link[12] & out_link[13];
C5L4_or_out = C5L4_p1_out # C5L4_p2_out # C5L4_p3_out # C5L4_p4_out;
C5L4 = C5L4_or_out;


--C4L41 is lpm_add_sub:i_rtl_1|addcore:adder[0]|prop_node[3]~77 at LC7
C4L41_p1_out = add_num[7] & add_num[6];
C4L41_p2_out = add_num[7] & out_link[6];
C4L41_p3_out = add_num[6] & out_link[7];
C4L41_p4_out = out_link[6] & out_link[7];
C4L41_or_out = C4L41_p1_out # C4L41_p2_out # C4L41_p3_out # C4L41_p4_out;
C4L41 = C4L41_or_out;


--C4L1 is lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~29 at SEXP21
C4L1 = EXP(!add_num[5] & !out_link[5]);


--C4L2 is lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~30 at SEXP23
C4L2 = EXP(!add_num[4] & !out_link[4]);


--C4L3 is lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~31 at SEXP24
C4L3 = EXP(!add_num[3] & !out_link[3]);


--C4L4 is lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~32 at SEXP25
C4L4 = EXP(!add_num[2] & !out_link[2]);


--C4L5 is lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~33 at SEXP26
C4L5 = EXP(!add_num[1] & !out_link[1]);


--C4L6 is lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~39 at LC18
C4L6_p0_out = C4L1 & C4L2 & C4L3 & C4L4 & C4L5 & add_num[0] & out_link[0];
C4L6_p1_out = C4L1 & add_num[4] & out_link[4];
C4L6_p2_out = C4L1 & C4L2 & add_num[3] & out_link[3];
C4L6_p3_out = C4L1 & C4L2 & C4L3 & add_num[2] & out_link[2];
C4L6_p4_out = C4L1 & C4L2 & C4L3 & C4L4 & add_num[1] & out_link[1];
C4L6_or_out = C4L7 # C4L6_p0_out # C4L6_p1_out # C4L6_p2_out # C4L6_p3_out # C4L6_p4_out;
C4L6 = C4L6_or_out;


--C5L2 is lpm_add_sub:i_rtl_1|addcore:adder[1]|genr_node[3]~91 at LC46
C5L2_p1_out = add_num[15] & out_link[15];
C5L2_p2_out = add_num[15] & add_num[14] & out_link[14];
C5L2_p3_out = out_link[15] & add_num[14] & out_link[14];