📄 ryxiangwei.map.rpt
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Analysis & Synthesis report for ryxiangwei
Mon Nov 01 22:58:28 2004
Version 4.0 Build 190 1/28/2004 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Default Parameter Settings
5. Hierarchy
6. Analysis & Synthesis Resource Utilization by Entity
7. Analysis & Synthesis Equations
8. Analysis & Synthesis Files Read
9. Analysis & Synthesis Resource Usage Summary
10. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2004 Altera Corporation
Any megafunction design, and related netlist (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only
to program PLD devices (but not masked PLD devices) from Altera. Any
other use of such megafunction design, netlist, support information,
device programming or simulation file, or any other related documentation
or information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to the
intellectual property, including patents, copyrights, trademarks, trade
secrets, or maskworks, embodied in any such megafunction design, netlist,
support information, device programming or simulation file, or any other
related documentation or information provided by Altera or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
+---------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+---------------------------------------+
; Analysis & Synthesis Status ; Successful - Mon Nov 01 22:58:28 2004 ;
; Revision Name ; ryxiangwei ;
; Top-level Entity Name ; ryxiangwei ;
; Family ; MAX7000S ;
; Total macrocells ; 122 ;
; Total pins ; 20 ;
+-----------------------------+---------------------------------------+
+-----------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+------------------------------------------------------------------------------------------------------
; Option ; Setting ; Default Value ;
+----------------------------------------------------------------------+--------------+---------------+
; Use Generated Physical Constraints File ; On ; ;
; Physical Synthesis Level for Resynthesis ; Normal ; ;
; Resynthesis Optimization Effort ; Normal ; ;
; Type of Retiming Performed During Resynthesis ; Full ; ;
; Optimization Technique -- MAX 7000B/7000AE/3000A ; Area ; Speed ;
; Top-level entity name ; ryxiangwei ; ;
; Family name ; MAX7000S ; Stratix ;
; Auto Resource Sharing ; Off ; Off ;
; Remove Duplicate Logic ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto Parallel Expanders ; On ; On ;
; Parallel Expander Chain Length -- MAX 7000B/7000AE/3000A/7000S/7000A ; 4 ; 4 ;
; Auto Logic Cell Insertion ; On ; On ;
; Allow XOR Gate Usage ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Ignore SOFT Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Off ; Off ;
; Ignore LCELL Buffers -- MAX 7000B/7000AE/3000A/7000S/7000A ; Auto ; Auto ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore CARRY Buffers ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Power-Up Don't Care ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; State Machine Processing ; Auto ; Auto ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; Preserve fewer node names ; On ; On ;
; Disk space/compilation speed tradeoff ; Normal ; Normal ;
; Create Debugging Nodes for IP Cores ; off ; off ;
+----------------------------------------------------------------------+--------------+---------------+
+-------------------------------------------------+
; Analysis & Synthesis Default Parameter Settings ;
+--------------------------------------------------
; Name ; Setting ;
+--------------------+----------------------------+
; CARRY_CHAIN ; MANUAL ;
; CASCADE_CHAIN ; MANUAL ;
; OPTIMIZE_FOR_SPEED ; 1 ;
; STYLE ; FAST ;
+--------------------+----------------------------+
+------------+
; Hierarchy ;
+------------+
ryxiangwei
|-- lpm_add_sub:i_rtl_0
|-- addcore:adder
|-- addcore:adder[0]
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- look_add:look_ahead_unit
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
|-- lpm_add_sub:i_rtl_1
|-- addcore:adder
|-- addcore:adder[0]
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- addcore:adder[1]
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- addcore:adder[2]
|-- a_csnbuffer:cout_node
|-- a_csnbuffer:oflow_node
|-- a_csnbuffer:result_node
|-- altshift:carry_ext_latency_ffs
|-- look_add:look_ahead_unit
|-- altshift:oflow_ext_latency_ffs
|-- altshift:result_ext_latency_ffs
+-----------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+------------------------------------------------------------------------------------------------------------------
; Compilation Hierarchy Node ; Macrocells ; Pins ; Full Hierarchy Name ;
+----------------------------------+------------+------+----------------------------------------------------------+
; |ryxiangwei ; 122 ; 20 ; |ryxiangwei ;
; |lpm_add_sub:i_rtl_0| ; 15 ; 0 ; |ryxiangwei|lpm_add_sub:i_rtl_0 ;
; |addcore:adder[0]| ; 12 ; 0 ; |ryxiangwei|lpm_add_sub:i_rtl_0|addcore:adder[0] ;
; |lpm_add_sub:i_rtl_1| ; 24 ; 0 ; |ryxiangwei|lpm_add_sub:i_rtl_1 ;
; |addcore:adder[0]| ; 11 ; 0 ; |ryxiangwei|lpm_add_sub:i_rtl_1|addcore:adder[0] ;
; |addcore:adder[1]| ; 10 ; 0 ; |ryxiangwei|lpm_add_sub:i_rtl_1|addcore:adder[1] ;
; |look_add:look_ahead_unit| ; 3 ; 0 ; |ryxiangwei|lpm_add_sub:i_rtl_1|look_add:look_ahead_unit ;
+----------------------------------+------------+------+----------------------------------------------------------+
+---------------------------------+
; Analysis & Synthesis Equations ;
+---------------------------------+
The equations can be found in D:/Modeltech_5.7g/examples/ryxiangwei/ryxiangwei.map.eqn.
+-----------------------------------------------------------+
; Analysis & Synthesis Files Read ;
+------------------------------------------------------------
; File Name ; Read ;
+----------------------------------------------------+------+
; ryxiangwei.v ; Read ;
; h:/quartus/libraries/megafunctions/lpm_add_sub.tdf ; Read ;
; h:/quartus/libraries/megafunctions/addcore.tdf ; Read ;
; h:/quartus/libraries/megafunctions/a_csnbuffer.tdf ; Read ;
; h:/quartus/libraries/megafunctions/look_add.tdf ; Read ;
; h:/quartus/libraries/megafunctions/altshift.tdf ; Read ;
+----------------------------------------------------+------+
+---------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+----------------------------------------------
; Resource ; Usage ;
+----------------------+----------------------+
; Logic cells ; 122 ;
; Total registers ; 81 ;
; I/O pins ; 20 ;
; Shareable expanders ; 35 ;
; Parallel expanders ; 7 ;
; Maximum fan-out node ; Load ;
; Maximum fan-out ; 66 ;
; Total fan-out ; 833 ;
; Average fan-out ; 4.71 ;
+----------------------+----------------------+
+--------------------------------+
; Analysis & Synthesis Messages ;
+--------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 4.0 Build 190 1/28/2004 SJ Full Version
Info: Processing started: Mon Nov 01 22:57:27 2004
Info: Command: quartus_map --import_settings_files=on --export_settings_files=off ryxiangwei -c ryxiangwei
Warning: Verilog HDL warning at ryxiangwei.v(12): using specified range for net, port, or variable out_addr that was previously declared without a range specification
Warning: Verilog HDL warning at ryxiangwei.v(19): using specified range for net, port, or variable gate that was previously declared without a range specification
Info: Found 1 design units and 1 entities in source file ryxiangwei.v
Info: Found entity 1: ryxiangwei
Info: Found 1 design units and 1 entities in source file h:/quartus/libraries/megafunctions/lpm_add_sub.tdf
Info: Found entity 1: lpm_add_sub
Info: Found 1 design units and 1 entities in source file h:/quartus/libraries/megafunctions/addcore.tdf
Info: Found entity 1: addcore
Info: Found 1 design units and 1 entities in source file h:/quartus/libraries/megafunctions/a_csnbuffer.tdf
Info: Found entity 1: a_csnbuffer
Info: Found 1 design units and 1 entities in source file h:/quartus/libraries/megafunctions/look_add.tdf
Info: Found entity 1: look_add
Info: Found 1 design units and 1 entities in source file h:/quartus/libraries/megafunctions/altshift.tdf
Info: Found entity 1: altshift
Info: Ignored 24 buffer(s)
Info: Ignored 24 SOFT buffer(s)
Info: Promoted pin-driven signal(s) to global signal
Info: Promoted clock signal driven by pin clk to global clock signal
Info: Implemented 177 device resources after synthesis - the final resource count might be different
Info: Implemented 4 input pins
Info: Implemented 16 output pins
Info: Implemented 122 macrocells
Info: Implemented 35 shareable expanders
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Processing ended: Mon Nov 01 22:58:28 2004
Info: Elapsed time: 00:01:01
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