📄 ryxiangwei.fit.rpt
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; PIA buffers ; 139 / 288 ( 48 % ) ;
; PIAs ; 151 / 288 ( 52 % ) ;
+----------------------------+--------------------+
+-----------------------------------------------------------------------------+
; LAB External Interconnect ;
+-----------------------------------------------+-----------------------------+
; LAB External Interconnects (Average = 18.88) ; Number of LABs (Total = 8) ;
+-----------------------------------------------+-----------------------------+
; 0 - 2 ; 0 ;
; 3 - 5 ; 0 ;
; 6 - 8 ; 0 ;
; 9 - 11 ; 1 ;
; 12 - 14 ; 1 ;
; 15 - 17 ; 2 ;
; 18 - 20 ; 1 ;
; 21 - 23 ; 0 ;
; 24 - 26 ; 2 ;
; 27 - 29 ; 1 ;
+-----------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------+
; LAB Macrocells ;
+-----------------------------------------+-----------------------------+
; Number of Macrocells (Average = 15.25) ; Number of LABs (Total = 8) ;
+-----------------------------------------+-----------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 2 ;
; 15 ; 2 ;
; 16 ; 4 ;
+-----------------------------------------+-----------------------------+
+---------------------------------------------------------+
; Parallel Expander ;
+--------------------------+------------------------------+
; Parallel Expander Length ; Number of Parallel Expanders ;
+--------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 7 ;
+--------------------------+------------------------------+
+-------------------------------------------------------------------------------+
; Shareable Expander ;
+-------------------------------------------------+-----------------------------+
; Number of shareable expanders (Average = 4.50) ; Number of LABs (Total = 6) ;
+-------------------------------------------------+-----------------------------+
; 0 ; 2 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 1 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 1 ;
+-------------------------------------------------+-----------------------------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Logic Cell Interconnection ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
; LAB ; Logic Cell ; Input ; Output ;
+-----+------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; A ; LC9 ; clk, Load, add_num[8], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00004~4, out_link[8] ; lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~389, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~396, lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[6]~85, lpm_add_sub:i_rtl_1|addcore:adder[1]|gc[2]~66, lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[1]~94, lpm_add_sub:i_rtl_1|addcore:adder[1]|unreg_res_node[1]~61, add_num[8] ;
; A ; LC10 ; clk, Load, lpm_add_sub:i_rtl_1|addcore:adder[1]|unreg_res_node[1]~61 ; lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~388, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~396, lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[6]~85, lpm_add_sub:i_rtl_1|addcore:adder[1]|gc[2]~66, lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[1]~94, lpm_add_sub:i_rtl_1|addcore:adder[1]|unreg_res_node[1]~60 ;
; A ; LC11 ; add_num[8], out_link[8], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~389, add_num[7], out_link[7], lpm_add_sub:i_rtl_1|addcore:adder[0]|prop_node[3]~77, lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~39, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~390, add_num[6], out_link[6], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~388, lpm_add_sub:i_rtl_1|addcore:adder[1]|unreg_res_node[1]~60 ; add_num[9] ;
; A ; LC12 ; clk, Load, out_link[10], add_num[10], lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[1]~94 ; lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~387, lpm_add_sub:i_rtl_1|addcore:adder[1]|gc[2]~66, add_num[10], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~397, lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[6]~95 ;
; A ; LC14 ; add_num[9], out_link[9], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~388, add_num[8], out_link[8], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~389, add_num[7], out_link[7], lpm_add_sub:i_rtl_1|addcore:adder[0]|prop_node[3]~77, lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~39, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~390, add_num[6], out_link[6] ; add_num[10] ;
; A ; LC15 ; clk, lpm_add_sub:i_rtl_1|addcore:adder[1]|pc[2]~73, add_num[11], Load, lpm_add_sub:i_rtl_1|addcore:adder[1]|gc[2]~66, out_link[11] ; lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~386, add_num[11], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~397, lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[6]~95 ;
; A ; LC16 ; add_num[10], out_link[10], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~387, add_num[9], out_link[9], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~388, add_num[8], out_link[8] ; add_num[11] ;
; A ; LC13 ; lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~389, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~388, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~387, add_num[7], out_link[7], lpm_add_sub:i_rtl_1|addcore:adder[0]|prop_node[3]~77, lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~39, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~390, add_num[6], out_link[6] ; add_num[11] ;
; A ; LC5 ; clk, Load, out_link[7], add_num[7], lpm_add_sub:i_rtl_1|addcore:adder[0]|tot_cin_node[6]~11 ; lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~390, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~396, lpm_add_sub:i_rtl_1|addcore:adder[0]|prop_node[3]~77, lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[6]~85, lpm_add_sub:i_rtl_1|addcore:adder[1]|pc[2]~73, lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[1]~94, lpm_add_sub:i_rtl_1|addcore:adder[1]|unreg_res_node[1]~61, add_num[7], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00004~4 ;
; A ; LC4 ; lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[6]~95, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~386, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~387, add_num[9], out_link[9], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~388, add_num[8], out_link[8], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~389, add_num[7], out_link[7], lpm_add_sub:i_rtl_1|addcore:adder[0]|prop_node[3]~77, lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~39, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~390, add_num[6], out_link[6] ; lpm_add_sub:i_rtl_1|addcore:adder[1]|unreg_res_node[7]~50, i76~11, add_num[14], add_num[13], add_num[12], i76~18 ;
; A ; LC2 ; lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~397, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~386, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~387, add_num[9], lpm_add_sub:i_rtl_1|addcore:adder[1]|prop_node[3]~100, lpm_add_sub:i_rtl_1|addcore:adder[1]|prop_node[2]~105, out_link[9], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~388, add_num[8], out_link[8], lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~389, add_num[7], out_link[7], lpm_add_sub:i_rtl_1|addcore:adder[0]|prop_node[3]~77, lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~39, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~390, add_num[6], out_link[6] ; lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[7]~118, out_addr[7]~reg0, lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[2]~39, lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[2]~47, lpm_add_sub:i_rtl_0|addcore:adder[0]|g3~1, lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[1]~54, lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[2]~156, out_addr[1]~reg0, lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[1]~168, out_addr[0]~reg0, gate[7]~reg0, gate[6]~reg0, gate[5]~reg0, gate[4]~reg0, gate[3]~reg0, gate[2]~reg0, gate[1]~reg0, gate[0]~reg0, lpm_add_sub:i_rtl_0|addcore:adder[0]|ps[6]~57, lpm_add_sub:i_rtl_0|addcore:adder[0]|ps[5]~62, lpm_add_sub:i_rtl_0|addcore:adder[0]|ps[4]~67, lpm_add_sub:i_rtl_0|addcore:adder[0]|g4~2, lpm_add_sub:i_rtl_0|datab_node[4]~49, add_num[23], add_num[22], add_num[21], add_num[20], add_num[19], add_num[18], add_num[17], add_num[16], lpm_add_sub:i_rtl_0|datab_node[6]~65, lpm_add_sub:i_rtl_0|datab_node[5]~69, lpm_add_sub:i_rtl_0|addcore:adder[0]|unreg_res_node[7]~180, lpm_add_sub:i_rtl_0|addcore:adder[0]|gc[2]~55, lpm_add_sub:i_rtl_0|addcore:adder[0]|g3~6sexp1bal ;
; A ; LC7 ; add_num[7], add_num[6], out_link[6], out_link[7] ; lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~396, lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[6]~85, lpm_add_sub:i_rtl_1|addcore:adder[1]|pc[2]~73, lpm_add_sub:i_rtl_1|addcore:adder[1]|tot_cin_node[1]~94, lpm_add_sub:i_rtl_1|addcore:adder[1]|unreg_res_node[1]~61, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00004~4 ;
; A ; LC8 ; add_num[13], add_num[12], out_link[12], out_link[13] ; lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~396, lpm_add_sub:i_rtl_1|look_add:look_ahead_unit|$00005~397 ;
; A ; LC6 ; add_num[7], out_link[7], add_num[6], out_link[6], lpm_add_sub:i_rtl_1|addcore:adder[0]|prop_node[3]~77, lpm_add_sub:i_rtl_1|addcore:adder[0]|bg_out~39
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