ryxiangwei.qsf

数字相位计实现

# Copyright (C) 1991-2004 Altera Corporation
# Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
# support information,  device programming or simulation file,  and any other
# associated  documentation or information  provided by  Altera  or a partner
# under  Altera's   Megafunction   Partnership   Program  may  be  used  only
# to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
# other  use  of such  megafunction  design,  netlist,  support  information,
# device programming or simulation file,  or any other  related documentation
# or information  is prohibited  for  any  other purpose,  including, but not
# limited to  modification,  reverse engineering,  de-compiling, or use  with
# any other  silicon devices,  unless such use is  explicitly  licensed under
# a separate agreement with  Altera  or a megafunction partner.  Title to the
# intellectual property,  including patents,  copyrights,  trademarks,  trade
# secrets,  or maskworks,  embodied in any such megafunction design, netlist,
# support  information,  device programming or simulation file,  or any other
# related documentation or information provided by  Altera  or a megafunction
# partner, remains with Altera, the megafunction partner, or their respective
# licensors. No other licenses, including any licenses needed under any third
# party's intellectual property, are provided herein.


# The default values for assignments are stored in the file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


# Project-Wide Assignments
# ========================
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 4.0
set_global_assignment -name PROJECT_CREATION_TIME_DATE "20:40:48  OCTOBER 03, 2004"
set_global_assignment -name LAST_QUARTUS_VERSION 4.0
set_global_assignment -name VERILOG_FILE ryxiangwei.v

# Pin & Location Assignments
# ==========================
set_location_assignment PIN_27 -to mode
set_location_assignment PIN_28 -to reset
set_location_assignment PIN_30 -to Txd
set_location_assignment PIN_31 -to Rxd
set_location_assignment PIN_45 -to out_addr\[0\]
set_location_assignment PIN_46 -to out_addr\[1\]
set_location_assignment PIN_48 -to out_addr\[2\]
set_location_assignment PIN_49 -to out_addr\[3\]
set_location_assignment PIN_50 -to out_addr\[4\]
set_location_assignment PIN_51 -to out_addr\[5\]
set_location_assignment PIN_83 -to clk
set_location_assignment PIN_29 -to Load
set_location_assignment PIN_35 -to xiang_reg
set_location_assignment PIN_52 -to out_addr\[6\]
set_location_assignment PIN_54 -to out_addr\[7\]
set_location_assignment PIN_58 -to out_addr\[8\]
set_location_assignment PIN_60 -to gate\[0\]
set_location_assignment PIN_61 -to gate\[1\]
set_location_assignment PIN_63 -to gate\[2\]
set_location_assignment PIN_64 -to gate\[3\]
set_location_assignment PIN_65 -to gate\[4\]
set_location_assignment PIN_67 -to gate\[5\]
set_location_assignment PIN_68 -to gate\[6\]
set_location_assignment PIN_69 -to gate\[7\]

# Analysis & Synthesis Assignments
# ================================
set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name TOP_LEVEL_ENTITY ryxiangwei

# Fitter Assignments
# ==================
set_global_assignment -name OPTIMIZE_TIMING "NORMAL COMPILATION"
set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
set_global_assignment -name DEVICE "EPM7128SLC84-15"

# EDA Netlist Writer Assignments
# ==============================
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog HDL output from Quartus II)"

# ---------------------------------------
# start EDA_TOOL_SETTINGS(eda_simulation)

	# EDA Netlist Writer Assignments
	# ==============================
	set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation

# end EDA_TOOL_SETTINGS(eda_simulation)
# -------------------------------------