hymod.c

U BOOT源码

	 * Initialise the FS6377 clock chip
	 *
	 * the secondary address is the register number from where to
	 * start the write - I want to write all the registers
	 *
	 * don't bother checking return status - we have no console yet
	 * to print it on, nor any RAM to store it in - it will be obvious
	 * if this doesn't work
	 */
	(void) i2c_write (fs6377_addr, 0, 1, fs6377_regs,
					sizeof (fs6377_regs));

	return (0);
}

/* ------------------------------------------------------------------------- */

/*
 * Check Board Identity: Hardwired to HYMOD
 */

int
checkboard (void)
{
	puts ("Board: HYMOD\n");
	return (0);
}

/* ------------------------------------------------------------------------- */

/*
 * miscellaneous (early - while running in flash) initialisations.
 */

#define _NOT_USED_	0xFFFFFFFF

uint upmb_table[] = {
	/* Read Single Beat (RSS) - offset 0x00 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/* Read Burst (RBS) - offset 0x08 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/* Write Single Beat (WSS) - offset 0x18 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/* Write Burst (WSS) - offset 0x20 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/* Refresh Timer (PTS) - offset 0x30 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/* Exception Condition (EXS) - offset 0x3c */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
};

uint upmc_table[] = {
	/* Read Single Beat (RSS) - offset 0x00 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/* Read Burst (RBS) - offset 0x08 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/* Write Single Beat (WSS) - offset 0x18 */
	0xF0E00000, 0xF0A00000, 0x00A00000, 0x30A00000,
	0xF0F40007, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/* Write Burst (WSS) - offset 0x20 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/* Refresh Timer (PTS) - offset 0x30 */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
	/* Exception Condition (EXS) - offset 0x3c */
	_NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_
};

int
misc_init_f (void)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;

	printf ("UPMs:  ");

	upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
	memctl->memc_mbmr = CFG_MBMR;

	upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
	memctl->memc_mcmr = CFG_MCMR;

	printf ("configured\n");
	return (0);
}

/* ------------------------------------------------------------------------- */

long
initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CFG_IMMR;
	volatile memctl8260_t *memctl = &immap->im_memctl;
	volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
	ulong psdmr = CFG_PSDMR;
	int i;

	/*
	 * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
	 *
	 * "At system reset, initialization software must set up the
	 *  programmable parameters in the memory controller banks registers
	 *  (ORx, BRx, P/LSDMR). After all memory parameters are con辡ured,
	 *  system software should execute the following initialization sequence
	 *  for each SDRAM device.
	 *
	 *  1. Issue a PRECHARGE-ALL-BANKS command
	 *  2. Issue eight CBR REFRESH commands
	 *  3. Issue a MODE-SET command to initialize the mode register
	 *
	 *  The initial commands are executed by setting P/LSDMR[OP] and
	 *  accessing the SDRAM with a single-byte transaction."
	 *
	 * The appropriate BRx/ORx registers have already been set when we
	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
	 */

	memctl->memc_psrt = CFG_PSRT;
	memctl->memc_mptpr = CFG_MPTPR;

	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
	*ramaddr = c;

	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR;
	for (i = 0; i < 8; i++)
		*ramaddr = c;

	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
	*ramaddr = c;

	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
	*ramaddr = c;

	return (CFG_SDRAM_SIZE << 20);
}

/* ------------------------------------------------------------------------- */
/* miscellaneous initialisations after relocation into ram (misc_init_r)     */
/* 									     */
/* loads the data in the main board and mezzanine board eeproms into	     */
/* the hymod configuration struct stored in the board information area.	     */
/* 									     */
/* if the contents of either eeprom is invalid, prompts for a serial	     */
/* number (and an ethernet address if required) then fetches a file	     */
/* containing information to be stored in the eeprom from the tftp server    */
/* (the file name is based on the serial number and a built-in path)	     */

int
last_stage_init (void)
{
	DECLARE_GLOBAL_DATA_PTR;

	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
	int rc;

#ifdef CONFIG_BOOT_RETRY_TIME
	/*
	 * we use the readline () function, but we also want
	 * command timeout enabled
	 */
	init_cmd_timeout ();
#endif

	memset ((void *) cp, 0, sizeof (*cp));

	/* set up main board config info */

	rc = hymod_eeprom_read (0, &cp->main.eeprom);

	puts ("EEPROM:main...");
	if (rc < 0)
		puts ("NOT PRESENT\n");
	else if (rc == 0)
		puts ("INVALID\n");
	else {
		cp->main.eeprom.valid = 1;

		printf ("OK (ver %u)\n", cp->main.eeprom.ver);
		hymod_eeprom_print (&cp->main.eeprom);

		/*
		 * hard-wired assumption here: all hymod main boards will have
		 * one xilinx fpga, with the interrupt line connected to IRQ2
		 *
		 * One day, this might be based on the board type
		 */

		cp->main.xlx[0].mmap.prog.exists = 1;
		cp->main.xlx[0].mmap.prog.size = FPGA_MAIN_CFG_SIZE;
		cp->main.xlx[0].mmap.prog.base = FPGA_MAIN_CFG_BASE;

		cp->main.xlx[0].mmap.reg.exists = 1;
		cp->main.xlx[0].mmap.reg.size = FPGA_MAIN_REG_SIZE;
		cp->main.xlx[0].mmap.reg.base = FPGA_MAIN_REG_BASE;

		cp->main.xlx[0].mmap.port.exists = 1;
		cp->main.xlx[0].mmap.port.size = FPGA_MAIN_PORT_SIZE;
		cp->main.xlx[0].mmap.port.base = FPGA_MAIN_PORT_BASE;

		cp->main.xlx[0].iopins.prog_pin.port = FPGA_MAIN_PROG_PORT;
		cp->main.xlx[0].iopins.prog_pin.pin = FPGA_MAIN_PROG_PIN;
		cp->main.xlx[0].iopins.prog_pin.flag = 1;
		cp->main.xlx[0].iopins.init_pin.port = FPGA_MAIN_INIT_PORT;
		cp->main.xlx[0].iopins.init_pin.pin = FPGA_MAIN_INIT_PIN;
		cp->main.xlx[0].iopins.init_pin.flag = 1;
		cp->main.xlx[0].iopins.done_pin.port = FPGA_MAIN_DONE_PORT;
		cp->main.xlx[0].iopins.done_pin.pin = FPGA_MAIN_DONE_PIN;
		cp->main.xlx[0].iopins.done_pin.flag = 1;
#ifdef FPGA_MAIN_ENABLE_PORT
		cp->main.xlx[0].iopins.enable_pin.port = FPGA_MAIN_ENABLE_PORT;
		cp->main.xlx[0].iopins.enable_pin.pin = FPGA_MAIN_ENABLE_PIN;
		cp->main.xlx[0].iopins.enable_pin.flag = 1;
#endif

		cp->main.xlx[0].irq = FPGA_MAIN_IRQ;
	}

	/* set up mezzanine board config info */

	rc = hymod_eeprom_read (1, &cp->mezz.eeprom);

	puts ("EEPROM:mezz...");
	if (rc < 0)
		puts ("NOT PRESENT\n");
	else if (rc == 0)
		puts ("INVALID\n");
	else {
		cp->main.eeprom.valid = 1;

		printf ("OK (ver %u)\n", cp->mezz.eeprom.ver);
		hymod_eeprom_print (&cp->mezz.eeprom);
	}

	cp->crc = crc32 (0, (unsigned char *)cp, offsetof (hymod_conf_t, crc));

	hymod_check_env ();

	return (0);
}