clkinit.c

U BOOT源码

#       endif
#       if (SCLK_BRG == 2)
	    *IM_BRGC3 = sclk_brg;
#       endif
#       if (SCLK_BRG == 3)
	    *IM_BRGC4 = sclk_brg;
#       endif
#       if (SCLK_BRG == 4)
	    *IM_BRGC5 = sclk_brg;
#       endif
#       if (SCLK_BRG == 5)
	    *IM_BRGC6 = sclk_brg;
#       endif
#       if (SCLK_BRG == 6)
	    *IM_BRGC7 = sclk_brg;
#       endif
#       if (SCLK_BRG == 7)
	    *IM_BRGC8 = sclk_brg;
#       endif

	/*
	 * Set reset on LRCLK BRG
	 */
#       if (LRCLK_BRG == 0)
	    *IM_BRGC1 = lrclk_brg;
#       endif
#       if (LRCLK_BRG == 1)
	    *IM_BRGC2 = lrclk_brg;
#       endif
#       if (LRCLK_BRG == 2)
	    *IM_BRGC3 = lrclk_brg;
#       endif
#       if (LRCLK_BRG == 3)
	    *IM_BRGC4 = lrclk_brg;
#       endif
#       if (LRCLK_BRG == 4)
	    *IM_BRGC5 = lrclk_brg;
#       endif
#       if (LRCLK_BRG == 5)
	    *IM_BRGC6 = lrclk_brg;
#       endif
#       if (LRCLK_BRG == 6)
	    *IM_BRGC7 = lrclk_brg;
#       endif
#       if (LRCLK_BRG == 7)
	    *IM_BRGC8 = lrclk_brg;
#       endif

	/*
	 * Clear reset on MCLK BRG
	 */
#       if (MCLK_BRG == 0)
	    *IM_BRGC1 = mclk_brg & ~CPM_BRG_RST;
#       endif
#       if (MCLK_BRG == 1)
	    *IM_BRGC2 = mclk_brg & ~CPM_BRG_RST;
#       endif
#       if (MCLK_BRG == 2)
	    *IM_BRGC3 = mclk_brg & ~CPM_BRG_RST;
#       endif
#       if (MCLK_BRG == 3)
	    *IM_BRGC4 = mclk_brg & ~CPM_BRG_RST;
#       endif
#       if (MCLK_BRG == 4)
	    *IM_BRGC5 = mclk_brg & ~CPM_BRG_RST;
#       endif
#       if (MCLK_BRG == 5)
	    *IM_BRGC6 = mclk_brg & ~CPM_BRG_RST;
#       endif
#       if (MCLK_BRG == 6)
	    *IM_BRGC7 = mclk_brg & ~CPM_BRG_RST;
#       endif
#       if (MCLK_BRG == 7)
	    *IM_BRGC8 = mclk_brg & ~CPM_BRG_RST;
#       endif

	/*
	 * Clear reset on SCLK BRG
	 */
#       if (SCLK_BRG == 0)
	    *IM_BRGC1 = sclk_brg & ~CPM_BRG_RST;
#       endif
#       if (SCLK_BRG == 1)
	    *IM_BRGC2 = sclk_brg & ~CPM_BRG_RST;
#       endif
#       if (SCLK_BRG == 2)
	    *IM_BRGC3 = sclk_brg & ~CPM_BRG_RST;
#       endif
#       if (SCLK_BRG == 3)
	    *IM_BRGC4 = sclk_brg & ~CPM_BRG_RST;
#       endif
#       if (SCLK_BRG == 4)
	    *IM_BRGC5 = sclk_brg & ~CPM_BRG_RST;
#       endif
#       if (SCLK_BRG == 5)
	    *IM_BRGC6 = sclk_brg & ~CPM_BRG_RST;
#       endif
#       if (SCLK_BRG == 6)
	    *IM_BRGC7 = sclk_brg & ~CPM_BRG_RST;
#       endif
#       if (SCLK_BRG == 7)
	    *IM_BRGC8 = sclk_brg & ~CPM_BRG_RST;
#       endif

	/*
	 * Clear reset on LRCLK BRG
	 */
#       if (LRCLK_BRG == 0)
	    *IM_BRGC1 = lrclk_brg & ~CPM_BRG_RST;
#       endif
#       if (LRCLK_BRG == 1)
	    *IM_BRGC2 = lrclk_brg & ~CPM_BRG_RST;
#       endif
#       if (LRCLK_BRG == 2)
	    *IM_BRGC3 = lrclk_brg & ~CPM_BRG_RST;
#       endif
#       if (LRCLK_BRG == 3)
	    *IM_BRGC4 = lrclk_brg & ~CPM_BRG_RST;
#       endif
#       if (LRCLK_BRG == 4)
	    *IM_BRGC5 = lrclk_brg & ~CPM_BRG_RST;
#       endif
#       if (LRCLK_BRG == 5)
	    *IM_BRGC6 = lrclk_brg & ~CPM_BRG_RST;
#       endif
#       if (LRCLK_BRG == 6)
	    *IM_BRGC7 = lrclk_brg & ~CPM_BRG_RST;
#       endif
#       if (LRCLK_BRG == 7)
	    *IM_BRGC8 = lrclk_brg & ~CPM_BRG_RST;
#       endif

	/*
	 * Restore the Interrupt state
	 */
	if (flag) {
	    enable_interrupts();
	}
#   else
	/*
	 * Reset the clocks
	 */
	Daq_BRG_Reset(MCLK_BRG);
	Daq_BRG_Reset(SCLK_BRG);
	Daq_BRG_Reset(LRCLK_BRG);
#   endif
}

void Daq_Start_Clocks(int sample_rate)

{
#ifdef TIGHTEN_UP_BRG_TIMING
    volatile immap_t *immr = (immap_t *)CFG_IMMR;

    register uint mclk_brg;       /* MCLK  BRG value */
    register uint sclk_brg;       /* SCLK  BRG value */
    register uint temp_lrclk_brg; /* Temporary LRCLK BRG value */
    register uint real_lrclk_brg; /* Permanent LRCLK BRG value */
    uint          lrclk_brg;      /* LRCLK BRG value */
    unsigned long flags;          /* Interrupt flags */
    uint          sclk_cnt;       /* SCLK count */
    uint          delay_cnt;      /* Delay count */
#endif

#   ifdef TIGHTEN_UP_BRG_TIMING
	/*
	 * Obtain the enabled MCLK BRG value
	 */
#       if (MCLK_BRG == 0)
	    mclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (MCLK_BRG == 1)
	    mclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (MCLK_BRG == 2)
	    mclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (MCLK_BRG == 3)
	    mclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (MCLK_BRG == 4)
	    mclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (MCLK_BRG == 5)
	    mclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (MCLK_BRG == 6)
	    mclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (MCLK_BRG == 7)
	    mclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif

	/*
	 * Obtain the enabled SCLK BRG value
	 */
#       if (SCLK_BRG == 0)
	    sclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (SCLK_BRG == 1)
	    sclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (SCLK_BRG == 2)
	    sclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (SCLK_BRG == 3)
	    sclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (SCLK_BRG == 4)
	    sclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (SCLK_BRG == 5)
	    sclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (SCLK_BRG == 6)
	    sclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (SCLK_BRG == 7)
	    sclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif

	/*
	 * Obtain the enabled LRCLK BRG value
	 */
#       if (LRCLK_BRG == 0)
	    lrclk_brg = (*IM_BRGC1 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (LRCLK_BRG == 1)
	    lrclk_brg = (*IM_BRGC2 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (LRCLK_BRG == 2)
	    lrclk_brg = (*IM_BRGC3 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (LRCLK_BRG == 3)
	    lrclk_brg = (*IM_BRGC4 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (LRCLK_BRG == 4)
	    lrclk_brg = (*IM_BRGC5 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (LRCLK_BRG == 5)
	    lrclk_brg = (*IM_BRGC6 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (LRCLK_BRG == 6)
	    lrclk_brg = (*IM_BRGC7 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif
#       if (LRCLK_BRG == 7)
	    lrclk_brg = (*IM_BRGC8 & ~CPM_BRG_RST) | CPM_BRG_EN;
#       endif

	/* Save off the real LRCLK value */
	real_lrclk_brg = lrclk_brg;

	/* Obtain the current SCLK count */
	sclk_cnt  = ((sclk_brg & 0x00001FFE) >> 1) + 1;

	/* Compute the delay as a function of SCLK count */
	delay_cnt = ((sclk_cnt / 4) - 2) * 10 + 6;
	if (DaqSampleRate == 43402) {
	  delay_cnt++;
	}

	/* Clear out the count */
	temp_lrclk_brg = sclk_brg & ~0x00001FFE;

	/* Insert the count */
	temp_lrclk_brg |= ((delay_cnt + (sclk_cnt / 2) - 1) << 1) &  0x00001FFE;

	/*
	 * Disable interrupt and save the current state
	 */
	flag = disable_interrupts();

	/*
	 * Enable MCLK BRG
	 */
#       if (MCLK_BRG == 0)
	    *IM_BRGC1 = mclk_brg;
#       endif
#       if (MCLK_BRG == 1)
	    *IM_BRGC2 = mclk_brg;
#       endif
#       if (MCLK_BRG == 2)
	    *IM_BRGC3 = mclk_brg;
#       endif
#       if (MCLK_BRG == 3)
	    *IM_BRGC4 = mclk_brg;
#       endif
#       if (MCLK_BRG == 4)
	    *IM_BRGC5 = mclk_brg;
#       endif
#       if (MCLK_BRG == 5)
	    *IM_BRGC6 = mclk_brg;
#       endif
#       if (MCLK_BRG == 6)
	    *IM_BRGC7 = mclk_brg;
#       endif
#       if (MCLK_BRG == 7)
	    *IM_BRGC8 = mclk_brg;
#       endif

	/*
	 * Enable SCLK BRG
	 */
#       if (SCLK_BRG == 0)
	    *IM_BRGC1 = sclk_brg;
#       endif
#       if (SCLK_BRG == 1)
	    *IM_BRGC2 = sclk_brg;
#       endif
#       if (SCLK_BRG == 2)
	    *IM_BRGC3 = sclk_brg;
#       endif
#       if (SCLK_BRG == 3)
	    *IM_BRGC4 = sclk_brg;
#       endif
#       if (SCLK_BRG == 4)
	    *IM_BRGC5 = sclk_brg;
#       endif
#       if (SCLK_BRG == 5)
	    *IM_BRGC6 = sclk_brg;
#       endif
#       if (SCLK_BRG == 6)
	    *IM_BRGC7 = sclk_brg;
#       endif
#       if (SCLK_BRG == 7)
	    *IM_BRGC8 = sclk_brg;
#       endif

	/*
	 * Enable LRCLK BRG (1st time - temporary)
	 */
#       if (LRCLK_BRG == 0)
	    *IM_BRGC1 = temp_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 1)
	    *IM_BRGC2 = temp_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 2)
	    *IM_BRGC3 = temp_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 3)
	    *IM_BRGC4 = temp_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 4)
	    *IM_BRGC5 = temp_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 5)
	    *IM_BRGC6 = temp_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 6)
	    *IM_BRGC7 = temp_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 7)
	    *IM_BRGC8 = temp_lrclk_brg;
#       endif

	/*
	 * Enable LRCLK BRG (2nd time - permanent)
	 */
#       if (LRCLK_BRG == 0)
	    *IM_BRGC1 = real_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 1)
	    *IM_BRGC2 = real_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 2)
	    *IM_BRGC3 = real_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 3)
	    *IM_BRGC4 = real_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 4)
	    *IM_BRGC5 = real_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 5)
	    *IM_BRGC6 = real_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 6)
	    *IM_BRGC7 = real_lrclk_brg;
#       endif
#       if (LRCLK_BRG == 7)
	    *IM_BRGC8 = real_lrclk_brg;
#       endif

	/*
	 * Restore the Interrupt state
	 */
	if (flag) {
	    enable_interrupts();
	}
#   else
	/*
	 * Enable the clocks
	 */
	Daq_BRG_Enable(LRCLK_BRG);
	Daq_BRG_Enable(SCLK_BRG);
	Daq_BRG_Enable(MCLK_BRG);
#   endif
}

void Daq_Display_Clocks(void)

{
    volatile immap_t *immr = (immap_t *)CFG_IMMR;
    uint mclk_divisor; /* Detected MCLK divisor */
    uint sclk_divisor; /* Detected SCLK divisor */

    printf("\nBRG:\n");
    if (immr->im_brgc4 != 0) {
	printf("\tbrgc4\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  MCLK\n",
	       immr->im_brgc4,
	       (uint)&(immr->im_brgc4),
	       Daq_BRG_Get_Count(3),
	       Daq_BRG_Get_ExtClk(3),
	       Daq_BRG_Get_ExtClk_Description(3));
    }
    if (immr->im_brgc8 != 0) {
	printf("\tbrgc8\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCLK\n",
	       immr->im_brgc8,
	       (uint)&(immr->im_brgc8),
	       Daq_BRG_Get_Count(7),
	       Daq_BRG_Get_ExtClk(7),
	       Daq_BRG_Get_ExtClk_Description(7));
    }
    if (immr->im_brgc6 != 0) {
	printf("\tbrgc6\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  LRCLK\n",
	       immr->im_brgc6,
	       (uint)&(immr->im_brgc6),
	       Daq_BRG_Get_Count(5),
	       Daq_BRG_Get_ExtClk(5),
	       Daq_BRG_Get_ExtClk_Description(5));
    }
    if (immr->im_brgc1 != 0) {
	printf("\tbrgc1\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC1\n",
	       immr->im_brgc1,
	       (uint)&(immr->im_brgc1),
	       Daq_BRG_Get_Count(0),
	       Daq_BRG_Get_ExtClk(0),
	       Daq_BRG_Get_ExtClk_Description(0));
    }
    if (immr->im_brgc2 != 0) {
	printf("\tbrgc2\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SMC2\n",
	       immr->im_brgc2,
	       (uint)&(immr->im_brgc2),
	       Daq_BRG_Get_Count(1),
	       Daq_BRG_Get_ExtClk(1),
	       Daq_BRG_Get_ExtClk_Description(1));
    }
    if (immr->im_brgc3 != 0) {
	printf("\tbrgc3\t0x%08x @ 0x%08x, %5d count, %d extc, %8s,  SCC1\n",
	       immr->im_brgc3,
	       (uint)&(immr->im_brgc3),
	       Daq_BRG_Get_Count(2),
	       Daq_BRG_Get_ExtClk(2),
	       Daq_BRG_Get_ExtClk_Description(2));
    }
    if (immr->im_brgc5 != 0) {
	printf("\tbrgc5\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
	       immr->im_brgc5,
	       (uint)&(immr->im_brgc5),
	       Daq_BRG_Get_Count(4),
	       Daq_BRG_Get_ExtClk(4),
	       Daq_BRG_Get_ExtClk_Description(4));
    }
    if (immr->im_brgc7 != 0) {
	printf("\tbrgc7\t0x%08x @ 0x%08x, %5d count, %d extc, %8s\n",
	       immr->im_brgc7,
	       (uint)&(immr->im_brgc7),
	       Daq_BRG_Get_Count(6),
	       Daq_BRG_Get_ExtClk(6),
	       Daq_BRG_Get_ExtClk_Description(6));
    }

#   ifdef RUN_SCLK_ON_BRG_INT
	mclk_divisor = Daq_BRG_Rate(MCLK_BRG) / Daq_BRG_Rate(SCLK_BRG);
#   else
	mclk_divisor = Daq_BRG_Get_Count(SCLK_BRG);
#   endif
#   ifdef RUN_LRCLK_ON_BRG_INT
	sclk_divisor = Daq_BRG_Rate(SCLK_BRG) / Daq_BRG_Rate(LRCLK_BRG);
#   else
	sclk_divisor = Daq_BRG_Get_Count(LRCLK_BRG);
#   endif

    printf("\nADC/DAC Clocking (%d/%d):\n", sclk_divisor, mclk_divisor);
    printf("\tMCLK  %8d Hz, or %3dx SCLK, or %3dx LRCLK\n",
	   Daq_BRG_Rate(MCLK_BRG),
	   mclk_divisor,
	   mclk_divisor * sclk_divisor);
#   ifdef RUN_SCLK_ON_BRG_INT
	printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
	       Daq_BRG_Rate(SCLK_BRG),
	       sclk_divisor);
#   else
	printf("\tSCLK  %8d Hz, or %3dx LRCLK\n",
	       Daq_BRG_Rate(MCLK_BRG) / mclk_divisor,
	       sclk_divisor);
#   endif
#   ifdef RUN_LRCLK_ON_BRG_INT
	printf("\tLRCLK %8d Hz\n",
	       Daq_BRG_Rate(LRCLK_BRG));
#   else
#       ifdef RUN_SCLK_ON_BRG_INT
	    printf("\tLRCLK %8d Hz\n",
		   Daq_BRG_Rate(SCLK_BRG) / sclk_divisor);
#       else
	    printf("\tLRCLK %8d Hz\n",
		   Daq_BRG_Rate(MCLK_BRG) / (mclk_divisor * sclk_divisor));
#       endif
#   endif
    printf("\n");
}