mb.h

U BOOT源码

/* MK48T02 RTC registers */
typedef
    struct {
	cma_mb_reg sram[2040];/* Battery-Backed SRAM */
	cma_mb_reg clk_ctl;	/* Clock Control Register */
	cma_mb_reg clk_sec;	/* Clock Seconds Register */
	cma_mb_reg clk_min;	/* Clock Minutes Register */
	cma_mb_reg clk_hour;	/* Clock Hour Register */
	cma_mb_reg clk_day;	/* Clock Day Register */
	cma_mb_reg clk_date;	/* Clock Date Register */
	cma_mb_reg clk_month;	/* Clock Month Register */
	cma_mb_reg clk_year;	/* Clock Year Register */
    }
cma_mb_rtc;

#endif

#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)

/* ST16C522 Serial I/O */
typedef
    struct {
	cma_mb_reg ser_rhr;	/* Receive Holding Register (R, DLAB=0) */
	cma_mb_reg ser_ier;	/* Interrupt Enable Register (R/W, DLAB=0) */
	cma_mb_reg ser_isr;	/* Interrupt Status Register (R) */
	cma_mb_reg ser_lcr;	/* Line Control Register (R/W) */
	cma_mb_reg ser_mcr;	/* Modem Control Register (R/W) */
	cma_mb_reg ser_lsr;	/* Line Status Register (R) */
	cma_mb_reg ser_msr;	/* Modem Status Register (R/W) */
	cma_mb_reg ser_spr;	/* Scratch Pad Register (R/W) */
    }
cma_mb_serial;

#define ser_thr	ser_rhr		/* Transmit Holding Register (W, DLAB=0) */
#define ser_brl	ser_rhr		/* Baud Rate Divisor Low Byte (R/W, DLAB=1) */
#define ser_brh	ser_ier		/* Baud Rate Divisor High Byte (R/W, DLAB=1) */
#define ser_fcr	ser_isr		/* FIFO Control Register (W) */
#define ser_nop	ser_lsr		/* No Operation (W) */

/* ST16C522 Parallel I/O */
typedef
    struct {
	cma_mb_reg par_rdr;	/* Port Read Data Register (R) */
	cma_mb_reg par_sr;	/* Status Register (R) */
	cma_mb_reg par_cmd;	/* Command Register (R) */
    }
cma_mb_parallel;

#define par_wdr	par_rdr		/* Port Write Data Register (W) */
#define par_ios	par_sr		/* I/O Select Register (W) */
#define par_ctl	par_cmd		/* Control Register (W) */

#endif

#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302)

/* HT6542B PS/2 Keyboard/Mouse Controller */
typedef
    struct {
	cma_mb_reg kbm_rdr;	/* Read Data Register (R) */
	cma_mb_reg kbm_sr;	/* Status Register (R) */
    }
cma_mb_kbm;

#define kbm_wdr	kbm_rdr		/* Write Data Register (W) */
#define kbm_cmd	kbm_sr		/* Command Register (W) */

#endif

#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)

/* HD44780 LCD Display */
typedef
    struct {
	cma_mb_reg lcd_ccr;	/* Current Character Register (R/W) */
	cma_mb_reg lcd_bsr;	/* Busy Status Register (R) */
    }
cma_mb_lcd;

#define lcd_cmd	lcd_bsr		/* Command Register (W) */

#endif

/* 8-Position Configuration Switch */
typedef
    struct {
	cma_mb_reg dip_val;	/* Dip Switch value (R) */
    }
cma_mb_dipsw;

#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)

/* V360EPC PCI Bridge */
typedef
    struct {
#if defined(__LITTLE_ENDIAN)
	unsigned short v3_pci_vendor;		/* 0x00 */
	unsigned short v3_pci_device;
	unsigned short v3_pci_cmd;		/* 0x04 */
	unsigned short v3_pci_stat;
	unsigned long  v3_pci_cc_rev;		/* 0x08 */
	unsigned long  v3_pci_hdr_cfg;		/* 0x0c */
	unsigned long  v3_pci_io_base;		/* 0x10 */
	unsigned long  v3_pci_base0;		/* 0x14 */
	unsigned long  v3_pci_base1;		/* 0x18 */
	unsigned long  reserved1[4];		/* 0x1c */
	unsigned short v3_pci_sub_vendor;	/* 0x2c */
	unsigned short v3_pci_sub_id;
	unsigned long  v3_pci_rom;		/* 0x30 */
	unsigned long  reserved2[2];		/* 0x34 */
	unsigned long  v3_pci_bparam;		/* 0x3c */
	unsigned long  v3_pci_map0;		/* 0x40 */
	unsigned long  v3_pci_map1;		/* 0x44 */
	unsigned long  v3_pci_int_stat;		/* 0x48 */
	unsigned long  v3_pci_int_cfg;		/* 0x4c */
	unsigned long  reserved3[1];		/* 0x50 */
	unsigned long  v3_lb_base0;		/* 0x54 */
	unsigned long  v3_lb_base1;		/* 0x58 */
	unsigned short reserved4;		/* 0x5c */
	unsigned short v3_lb_map0;
	unsigned short reserved5;		/* 0x60 */
	unsigned short v3_lb_map1;
	unsigned short v3_lb_base2;		/* 0x64 */
	unsigned short v3_lb_map2;
	unsigned long  v3_lb_size;		/* 0x68 */
	unsigned short reserved6;		/* 0x6c */
	unsigned short v3_lb_io_base;
	unsigned short v3_fifo_cfg;		/* 0x70 */
	unsigned short v3_fifo_priority;
	unsigned short v3_fifo_stat;		/* 0x74 */
	unsigned char  v3_lb_istat;
	unsigned char  v3_lb_imask;
	unsigned short v3_system;		/* 0x78 */
	unsigned short v3_lb_cfg;
	unsigned short v3_pci_cfg;		/* 0x7c */
	unsigned short reserved7;
	unsigned long  v3_dma_pci_addr0;	/* 0x80 */
	unsigned long  v3_dma_local_addr0;	/* 0x84 */
	unsigned long  v3_dma_length0:24;	/* 0x88 */
	unsigned long  v3_dma_csr0:8;
	unsigned long  v3_dma_ctlb_adr0;	/* 0x8c */
	unsigned long  v3_dma_pci_addr1;	/* 0x90 */
	unsigned long  v3_dma_local_addr1;	/* 0x94 */
	unsigned long  v3_dma_length1:24;	/* 0x98 */
	unsigned long  v3_dma_csr1:8;
	unsigned long  v3_dma_ctlb_adr1;	/* 0x9c */
	unsigned long  v3_i20_mups[8];		/* 0xa0 */
	unsigned char  v3_mail_data0;		/* 0xc0 */
	unsigned char  v3_mail_data1;
	unsigned char  v3_mail_data2;
	unsigned char  v3_mail_data3;
	unsigned char  v3_mail_data4;		/* 0xc4 */
	unsigned char  v3_mail_data5;
	unsigned char  v3_mail_data6;
	unsigned char  v3_mail_data7;
	unsigned char  v3_mail_data8;		/* 0xc8 */
	unsigned char  v3_mail_data9;
	unsigned char  v3_mail_data10;
	unsigned char  v3_mail_data11;
	unsigned char  v3_mail_data12;		/* 0xcc */
	unsigned char  v3_mail_data13;
	unsigned char  v3_mail_data14;
	unsigned char  v3_mail_data15;
	unsigned short v3_pci_mail_iewr;	/* 0xd0 */
	unsigned short v3_pci_mail_ierd;
	unsigned short v3_lb_mail_iewr;		/* 0xd4 */
	unsigned short v3_lb_mail_ierd;
	unsigned short v3_mail_wr_stat;		/* 0xd8 */
	unsigned short v3_mail_rd_stat;
	unsigned long  v3_qba_map;		/* 0xdc */
	unsigned long  v3_dma_delay:8;		/* 0xe0 */
	unsigned long  reserved8:24;
	unsigned long  reserved9[7];		/* 0xe4 */
#endif
#if defined(__BIG_ENDIAN)
	unsigned short v3_pci_device;		/* 0x00 */
	unsigned short v3_pci_vendor;
	unsigned short v3_pci_stat;		/* 0x04 */
	unsigned short v3_pci_cmd;
	unsigned long  v3_pci_cc_rev;		/* 0x08 */
	unsigned long  v3_pci_hdr_cfg;		/* 0x0c */
	unsigned long  v3_pci_io_base;		/* 0x10 */
	unsigned long  v3_pci_base0;		/* 0x14 */
	unsigned long  v3_pci_base1;		/* 0x18 */
	unsigned long  reserved1[4];		/* 0x1c */
	unsigned short v3_pci_sub_id;		/* 0x2c */
	unsigned short v3_pci_sub_vendor;
	unsigned long  v3_pci_rom;		/* 0x30 */
	unsigned long  reserved2[2];		/* 0x34 */
	unsigned long  v3_pci_bparam;		/* 0x3c */
	unsigned long  v3_pci_map0;		/* 0x40 */
	unsigned long  v3_pci_map1;		/* 0x44 */
	unsigned long  v3_pci_int_stat;		/* 0x48 */
	unsigned long  v3_pci_int_cfg;		/* 0x4c */
	unsigned long  reserved3;		/* 0x50 */
	unsigned long  v3_lb_base0;		/* 0x54 */
	unsigned long  v3_lb_base1;		/* 0x58 */
	unsigned short v3_lb_map0;		/* 0x5c */
	unsigned short reserved4;
	unsigned short v3_lb_map1;		/* 0x60 */
	unsigned short reserved5;
	unsigned short v3_lb_map2;		/* 0x64 */
	unsigned short v3_lb_base2;
	unsigned long  v3_lb_size;		/* 0x68 */
	unsigned short v3_lb_io_base;		/* 0x6c */
	unsigned short reserved6;
	unsigned short v3_fifo_priority;	/* 0x70 */
	unsigned short v3_fifo_cfg;
	unsigned char  v3_lb_imask;		/* 0x74 */
	unsigned char  v3_lb_istat;
	unsigned short v3_fifo_stat;
	unsigned short v3_lb_cfg;		/* 0x78 */
	unsigned short v3_system;
	unsigned short reserved7;		/* 0x7c */
	unsigned short v3_pci_cfg;
	unsigned long  v3_dma_pci_addr0;	/* 0x80 */
	unsigned long  v3_dma_local_addr0;	/* 0x84 */
	unsigned long  v3_dma_csr0:8;		/* 0x88 */
	unsigned long  v3_dma_length0:24;
	unsigned long  v3_dma_ctlb_adr0;	/* 0x8c */
	unsigned long  v3_dma_pci_addr1;	/* 0x90 */
	unsigned long  v3_dma_local_addr1;	/* 0x94 */
	unsigned long  v3_dma_csr1:8;		/* 0x98 */
	unsigned long  v3_dma_length1:24;
	unsigned long  v3_dma_ctlb_adr1;	/* 0x9c */
	unsigned long  v3_i20_mups[8];		/* 0xa0 */
	unsigned char  v3_mail_data3;		/* 0xc0 */
	unsigned char  v3_mail_data2;
	unsigned char  v3_mail_data1;
	unsigned char  v3_mail_data0;
	unsigned char  v3_mail_data7;		/* 0xc4 */
	unsigned char  v3_mail_data6;
	unsigned char  v3_mail_data5;
	unsigned char  v3_mail_data4;
	unsigned char  v3_mail_data11;		/* 0xc8 */
	unsigned char  v3_mail_data10;
	unsigned char  v3_mail_data9;
	unsigned char  v3_mail_data8;
	unsigned char  v3_mail_data15;		/* 0xcc */
	unsigned char  v3_mail_data14;
	unsigned char  v3_mail_data13;
	unsigned char  v3_mail_data12;
	unsigned short v3_pci_mail_ierd;	/* 0xd0 */
	unsigned short v3_pci_mail_iewr;
	unsigned short v3_lb_mail_ierd;		/* 0xd4 */
	unsigned short v3_lb_mail_iewr;
	unsigned short v3_mail_rd_stat;		/* 0xd8 */
	unsigned short v3_mail_wr_stat;
	unsigned long  v3_qba_map;		/* 0xdc */
	unsigned long  reserved8:24;		/* 0xe0 */
	unsigned long  v3_dma_delay:8;
	unsigned long  reserved9[7];		/* 0xe4 */
#endif
    }						/* 0x100 */
cma_mb_v360epc;

#endif

#endif	/* __ASSEMBLY__ */

#endif	/* _COGENT_MB_H */