mpsc.c

U BOOT源码

static int
galbrg_disable(int channel)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int temp;

	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP);
	temp &= 0xFFFEFFFF;
	GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG, channel, GALBRG_REG_GAP,temp);

	return 0;
}

static int
galbrg_set_clksrc(int channel, int value)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int temp;

	temp = GTREGREAD_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP);
	temp &= 0xFF83FFFF;
	temp |= (value << 18);
	GT_REG_WRITE_MIRROR(GALBRG_0_CONFREG,channel, GALBRG_REG_GAP,temp);

	return 0;
}

static int
galbrg_set_CUV(int channel, int value)
{
	GT_REG_WRITE(GALBRG_0_BTREG + (channel * GALBRG_REG_GAP), value);

	return 0;
}

#if 0
static int
galbrg_reset(int channel)
{
	unsigned int temp;

	temp = GTREGREAD(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP));
	temp |= 0x20000;
	GT_REG_WRITE(GALBRG_0_CONFREG + (channel * GALBRG_REG_GAP), temp);

	return 0;
}
#endif

static int
galsdma_set_RFT(int channel)
{
	unsigned int temp;

	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
	temp |= 0x00000001;
	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);

	return 0;
}

static int
galsdma_set_SFM(int channel)
{
	unsigned int temp;

	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
	temp |= 0x00000002;
	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);

	return 0;
}

static int
galsdma_set_rxle(int channel)
{
	unsigned int temp;

	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
	temp |= 0x00000040;
	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);

	return 0;
}

static int
galsdma_set_txle(int channel)
{
	unsigned int temp;

	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
	temp |= 0x00000080;
	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);

	return 0;
}

static int
galsdma_set_RC(int channel, unsigned int value)
{
	unsigned int temp;

	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
	temp &= ~0x0000003c;
	temp |= (value << 2);
	GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF), temp);

	return 0;
}

static int
galsdma_set_burstsize(int channel, unsigned int value)
{
	unsigned int temp;

	temp = GTREGREAD(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF));
	temp &= 0xFFFFCFFF;
	switch (value) {
	 case 8:
		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
			     (temp | (0x3 << 12)));
		break;

	 case 4:
		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
			     (temp | (0x2 << 12)));
		break;

	 case 2:
		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
			     (temp | (0x1 << 12)));
		break;

	 case 1:
		GT_REG_WRITE(GALSDMA_0_CONF_REG+(channel*GALSDMA_REG_DIFF),
			     (temp | (0x0 << 12)));
		break;

	 default:
		return -1;
		break;
	}

	return 0;
}

static int
galmpsc_connect(int channel, int connect)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int temp;

	temp = GTREGREAD_MIRROR_G(GALMPSC_ROUTING_REGISTER);

	if ((channel == 0) && connect)
		temp &= ~0x00000007;
	else if ((channel == 1) && connect)
		temp &= ~(0x00000007 << 6);
	else if ((channel == 0) && !connect)
		temp |= 0x00000007;
	else
		temp |= (0x00000007 << 6);

	/* Just in case... */
	temp &= 0x3fffffff;

	GT_REG_WRITE_MIRROR_G(GALMPSC_ROUTING_REGISTER, temp);

	return 0;
}

static int
galmpsc_route_serial(int channel, int connect)
{
	unsigned int temp;

	temp = GTREGREAD(GALMPSC_SERIAL_MULTIPLEX);

	if ((channel == 0) && connect)
		temp |= 0x00000100;
	else if ((channel == 1) && connect)
		temp |= 0x00001000;
	else if ((channel == 0) && !connect)
		temp &= ~0x00000100;
	else
		temp &= ~0x00001000;

	GT_REG_WRITE(GALMPSC_SERIAL_MULTIPLEX,temp);

	return 0;
}

static int
galmpsc_route_rx_clock(int channel, int brg)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int temp;

	temp = GTREGREAD_MIRROR_G(GALMPSC_RxC_ROUTE);

	if (channel == 0)
		temp |= brg;
	else
		temp |= (brg << 8);

	GT_REG_WRITE_MIRROR_G(GALMPSC_RxC_ROUTE,temp);

	return 0;
}

static int
galmpsc_route_tx_clock(int channel, int brg)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int temp;

	temp = GTREGREAD_MIRROR_G(GALMPSC_TxC_ROUTE);

	if (channel == 0)
		temp |= brg;
	else
		temp |= (brg << 8);

	GT_REG_WRITE_MIRROR_G(GALMPSC_TxC_ROUTE,temp);

	return 0;
}

static int
galmpsc_write_config_regs(int mpsc, int mode)
{
	if (mode == GALMPSC_UART) {
		/* Main config reg Low (Null modem, Enable Tx/Rx, UART mode) */
		GT_REG_WRITE(GALMPSC_MCONF_LOW + (mpsc*GALMPSC_REG_GAP),
			     0x000004c4);

		/* Main config reg High (32x Rx/Tx clock mode, width=8bits */
		GT_REG_WRITE(GALMPSC_MCONF_HIGH +(mpsc*GALMPSC_REG_GAP),
			     0x024003f8);
		/*        22 2222 1111 */
		/*        54 3210 9876 */
		/* 0000 0010 0000 0000 */
		/*       1 */
		/*       098 7654 3210 */
		/* 0000 0011 1111 1000 */
	} else
		return -1;

	return 0;
}

static int
galmpsc_config_channel_regs(int mpsc)
{
	DECLARE_GLOBAL_DATA_PTR;
	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, 0);
	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, 0);
	GT_REG_WRITE(GALMPSC_CHANNELREG_3+(mpsc*GALMPSC_REG_GAP), 1);
	GT_REG_WRITE(GALMPSC_CHANNELREG_4+(mpsc*GALMPSC_REG_GAP), 0);
	GT_REG_WRITE(GALMPSC_CHANNELREG_5+(mpsc*GALMPSC_REG_GAP), 0);
	GT_REG_WRITE(GALMPSC_CHANNELREG_6+(mpsc*GALMPSC_REG_GAP), 0);
	GT_REG_WRITE(GALMPSC_CHANNELREG_7+(mpsc*GALMPSC_REG_GAP), 0);
	GT_REG_WRITE(GALMPSC_CHANNELREG_8+(mpsc*GALMPSC_REG_GAP), 0);
	GT_REG_WRITE(GALMPSC_CHANNELREG_9+(mpsc*GALMPSC_REG_GAP), 0);
	GT_REG_WRITE(GALMPSC_CHANNELREG_10+(mpsc*GALMPSC_REG_GAP), 0);

	galmpsc_set_brkcnt(mpsc, 0x3);
	galmpsc_set_tcschar(mpsc, 0xab);

	return 0;
}

static int
galmpsc_set_brkcnt(int mpsc, int value)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int temp;

	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
	temp &= 0x0000FFFF;
	temp |= (value << 16);
	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp);

	return 0;
}

static int
galmpsc_set_tcschar(int mpsc, int value)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int temp;

	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP);
	temp &= 0xFFFF0000;
	temp |= value;
	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_1,mpsc,GALMPSC_REG_GAP, temp);

	return 0;
}

static int
galmpsc_set_char_length(int mpsc, int value)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int temp;

	temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
	temp &= 0xFFFFCFFF;
	temp |= (value << 12);
	GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP, temp);

	return 0;
}

static int
galmpsc_set_stop_bit_length(int mpsc, int value)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int temp;

	temp = GTREGREAD_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP);
	temp |= (value << 14);
	GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG,mpsc,GALMPSC_REG_GAP,temp);

	return 0;
}

static int
galmpsc_set_parity(int mpsc, int value)
{
	DECLARE_GLOBAL_DATA_PTR;
	unsigned int temp;

	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
	if (value != -1) {
		temp &= 0xFFF3FFF3;
		temp |= ((value << 18) | (value << 2));
		temp |= ((value << 17) | (value << 1));
	} else {
		temp &= 0xFFF1FFF1;
	}

	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp);

	return 0;
}

static int
galmpsc_enter_hunt(int mpsc)
{
	DECLARE_GLOBAL_DATA_PTR;
	int temp;

	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
	temp |= 0x80000000;
	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP, temp);

	/* Should Poll on Enter Hunt bit, but the register is write-only */
	/* errata suggests pausing 100 system cycles */
	udelay(100);

	return 0;
}


static int
galmpsc_shutdown(int mpsc)
{
	DECLARE_GLOBAL_DATA_PTR;
#if 0
	unsigned int temp;

	/* cause RX abort (clears RX) */
	temp = GTREGREAD_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP);
	temp |= MPSC_RX_ABORT | MPSC_TX_ABORT;
	temp &= ~MPSC_ENTER_HUNT;
	GT_REG_WRITE_MIRROR(GALMPSC_CHANNELREG_2,mpsc,GALMPSC_REG_GAP,temp);
#endif

	GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF, 0);
	GT_REG_WRITE(GALSDMA_0_COM_REG + CHANNEL * GALSDMA_REG_DIFF,
	             SDMA_TX_ABORT | SDMA_RX_ABORT);

	/* shut down the MPSC */
	GT_REG_WRITE(GALMPSC_MCONF_LOW, 0);
	GT_REG_WRITE(GALMPSC_MCONF_HIGH, 0);
	GT_REG_WRITE_MIRROR(GALMPSC_PROTOCONF_REG, mpsc, GALMPSC_REG_GAP,0);

	udelay(100);

	/* shut down the sdma engines. */
	/* reset config to default */
	GT_REG_WRITE(GALSDMA_0_CONF_REG + CHANNEL * GALSDMA_REG_DIFF,
	             0x000000fc);

	udelay(100);

	/* clear the SDMA current and first TX and RX pointers */
	GT_REG_WRITE(GALSDMA_0_CUR_RX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
	GT_REG_WRITE(GALSDMA_0_CUR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);
	GT_REG_WRITE(GALSDMA_0_FIR_TX_PTR + CHANNEL * GALSDMA_REG_DIFF, 0);

	udelay(100);

	return 0;
}

static void
galsdma_enable_rx(void)
{
	int temp;

	/* Enable RX processing */
	temp = GTREGREAD(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF));
	temp |= RX_ENABLE;
	GT_REG_WRITE(GALSDMA_0_COM_REG+(CHANNEL*GALSDMA_REG_DIFF), temp);

	galmpsc_enter_hunt(CHANNEL);
}

static int
galmpsc_set_snoop(int mpsc, int value)
{
	int reg = mpsc ? MPSC_1_ADDRESS_CONTROL_LOW : MPSC_0_ADDRESS_CONTROL_LOW;
	int temp=GTREGREAD(reg);
	if(value)
	    temp |= (1<< 6) | (1<<14) | (1<<22) | (1<<30);
	else
	    temp &= ~((1<< 6) | (1<<14) | (1<<22) | (1<<30));
	GT_REG_WRITE(reg, temp);
	return 0;
}