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📄 com_sub.cpp

📁 《WinCE.NET嵌入式工业用控制器及自动控制系统设计》的源代码
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		  if(PARA_IO[i].mod_no != I8052)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8052 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 53:
		  if(PARA_IO[i].mod_no != I8053)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8053 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 54:
		  if(PARA_IO[i].mod_no != I8054)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8054 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 55:
		  if(PARA_IO[i].mod_no != I8055)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8055 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 56:
		  if(PARA_IO[i].mod_no != I8056)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8056 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 57:
		  if(PARA_IO[i].mod_no != I8057)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8057 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 58:
		  if(PARA_IO[i].mod_no != I8058)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8058 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 60:
		  if(PARA_IO[i].mod_no != I8060)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8060 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 63:
		  if(PARA_IO[i].mod_no != I8063)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8063 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 64:
		  if(PARA_IO[i].mod_no != I8064)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8064 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 65:
		  if(PARA_IO[i].mod_no != I8065)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8065 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 66:
		  if(PARA_IO[i].mod_no != I8066)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8066 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 68:
		  if(PARA_IO[i].mod_no != I8068)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8068 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 69:
		  if(PARA_IO[i].mod_no != I8069)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8069 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 17:
		  if(PARA_IO[i].mod_no != I8017H)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8017H Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  case 24:
		  if(PARA_IO[i].mod_no != I8024)
		  {
			  rc= -1;
			  msg.Format(_T("Slot-%d is not define I-8024 Module"), slot);
			  AfxMessageBox(msg, MB_OK);
		  }
		  break;
	  default:
		  rc= -1;
		  msg.Format(_T("Slot-%d I-80%02d Module is not supported"), slot, temp);
		  AfxMessageBox(msg, MB_OK);
		  break;
	  }
  }
  if(rc != 0) return(-1);

//  DWORD ldata= GetDIOData32(1);
//  msg.Format(_T("I-8041: %08X"), ldata);
//  AfxMessageBox(msg, MB_OK);

  CUR_COUNT= 0;
  for(i=0; i<SLOT_MAX_CASE; i++)
   {
     if(PARA_IO[i].mod_no == 0) continue;  // empty slot
     slot= i+1;
     module= PARA_IO[i].mod_no;
     switch(module)
      {
        case I8017H:
	      chnl= IO_DEF[module -1].in_max;
          Init_8017H(slot);
          gain= PARA_IO[i].gain_ai; // signal input range
          mode= 0;  // polling mode
          for(m=0; m<chnl; m++)
            Set_8017H_Channel_Gain_Mode(slot, m,gain,mode);
          break;
        case I8024:
          I8024_Initial(slot);
          break;
      }
   }

// set H/W AO, DO initial output
   for(i=0; i<SLOT_MAX_CASE; i++)
   {
		if(PARA_IO[i].mod_no == 0) continue;   // empty slot
		slot= i+1;
		module= PARA_IO[i].mod_no;
		switch(module)
		{
		case I8024:  // 4 AO channel
			break;
		case I8041:  // 32 DO channel
        case I8042:  // 16 DI and 16 DO
        case I8056:  // 16 DO channel
        case I8057:
        case I8064:  // 8 DO channel
        case I8065:  // 8 DO channel
        case I8066:  // 8 DO channel
        case I8068:  // 8 DO channel
        case I8069:  // 8 DO channel
        case I8060:  // 6 channel DO
        case I8054:  // 8 DI and 8 DO
        case I8055:  
        case I8063:  // 4 DI and 4 DO
			chnl= IO_DEF[module -1].out_max;
			for(m=0; m<chnl; m++)
			{
			  addr= PARA_IO[i].addr_do -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  rc= Coil_Bit_Read(&Coil.DO_BARE[bytes], bitno);
			  fl= (float)rc;
			  set_AODO_output(DO_TYPE, addr, fl);
			}
			break;
		}

   }
   return(0);
}
/*...........................................................................*/
/* Get Local module value                                                    */
/*...........................................................................*/
void ICP_local_main(void)
{
  int i, m, n, slot, module, chnl_in, chnl_out, addr, gain, bytes, bitno;
  int  dd;
  unsigned short  data;
  unsigned char  bf[10];
  unsigned long  ldata;
  float  fl;
  int  idata[20];
  float fdata[20];
//  CString  msg;

  // check write request Queue QBUFF10
  while(1)
  {
	if(local_check_qbuff02() == -1)
		break;
  }

  // get AI channel data counting for delay time
  CUR_COUNT++;
  if(CUR_COUNT >= 2) CUR_COUNT=0;

  for(i=0; i<SLOT_MAX_CASE; i++)
   {
     if(PARA_IO[i].mod_no == 0) continue;  // empty slot
     slot= i+1;
     module= PARA_IO[i].mod_no;
     chnl_in= IO_DEF[module -1].in_max;
     chnl_out= IO_DEF[module -1].out_max;
     switch(module)
      {
        case I8017H:  // 8 AI channel
          gain= PARA_IO[i].gain_ai;  // signal input range
		  if(CUR_COUNT ==0)  
		  {
	          for(m=0; m<chnl_in; m++)
		       {
			     memset((char *)idata, 0, sizeof(idata));
				 memset((char *)fdata, 0, sizeof(fdata));
	             I8017H_AD_POLLING(slot, m, gain, 10, idata);
		         ARRAY_HEX_TO_FLOAT_ALL(idata, fdata, slot, gain, 10);
			     for(n=1, fl=0.0; n<9; n++)
				   fl= fl + fdata[n];
	             fl= fl / (float)8.0;  
		         addr= PARA_IO[i].addr_ai -1 +m;
			     if(addr < 0) continue;
				 else
		            Reg.AI_BARE[addr]= fl;
	           }
		  }
          break;
        case I8024:  // 4 AO channel
		  gain= PARA_IO[i].gain_ao;
          for(m=0; m<chnl_out; m++)
	       {
			 if(gain==0)
			     fl= I8024_VoltageOutReadBack(slot, m);
			 else
			     fl= I8024_CurrentOutReadBack(slot, m);
		    Reg.AO_BARE[addr]= fl;
		  }
          break;
        case I8052:  // 8 DI channel
        case I8058:
          bf[0]= DI_8(slot);
          for(m=0; m<chnl_in; m++)
           {
			  dd= Coil_Bit_Read(&bf[0], m);
              addr= PARA_IO[i].addr_di -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DI_BARE[bytes], bitno, dd);
           }
          break;  
        case I8051:  // 16 DI channel
        case I8053:
          data= DI_16(slot);
		  memcpy(bf, (char *)&data, 2);
          for(m=0; m<chnl_in; m++)
           {
			  if(m<8)
				dd= Coil_Bit_Read(&bf[0], m);
			  else
				dd= Coil_Bit_Read(&bf[1], m-8);
              addr= PARA_IO[i].addr_di -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DI_BARE[bytes], bitno, dd);
           }
          break;  
        case I8040:  // 32 DI channel
//          ldata= DI_32(slot);
          ldata= GetDIOData32(slot);
		  memcpy(bf, (char *)&ldata, 4);
          for(m=0; m<chnl_in; m++)
           {
			  if(m>=0 && m<=7)
				dd= Coil_Bit_Read(&bf[0], m);
			  else if(m>=8 && m<=15)
				dd= Coil_Bit_Read(&bf[1], m-8);
			  else if(m>=16 && m<=23)
				dd= Coil_Bit_Read(&bf[2], m-16);
			  else if(m>=24 && m<=31)
				dd= Coil_Bit_Read(&bf[3], m-24);
              addr= PARA_IO[i].addr_di -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DI_BARE[bytes], bitno, dd);
           }
          break;  
        case I8041:  // 32 DO channel
          ldata= GetDIOData32(slot);
		  memcpy(bf, (char *)&ldata, 4);
          for(m=0; m<chnl_out; m++)
           {
			  if(m>=0 && m<=7)
				dd= Coil_Bit_Read(&bf[0], m);
			  else if(m>=8 && m<=15)
				dd= Coil_Bit_Read(&bf[1], m-8);
			  else if(m>=16 && m<=23)
				dd= Coil_Bit_Read(&bf[2], m-16);
			  else if(m>=24 && m<=31)
				dd= Coil_Bit_Read(&bf[3], m-24);
              addr= PARA_IO[i].addr_do -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DO_BARE[bytes], bitno, dd);
           }
          break;  
        case I8042:  // 16 DI and 16 DO
          ldata= GetDIOData32(slot);
		  memcpy(bf, (char *)&ldata, 4);
          for(m=0; m<chnl_in; m++)
           {
			  if(m>=0 && m<=7)
				dd= Coil_Bit_Read(&bf[0], m);
			  else if(m>=8 && m<=15)
				dd= Coil_Bit_Read(&bf[1], m-8);
              addr= PARA_IO[i].addr_di -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DI_BARE[bytes], bitno, dd);
           }
          for(m=0; m<chnl_out; m++)
           {
			  if(m>=0 && m<=7)
				dd= Coil_Bit_Read(&bf[2], m);
			  else if(m>=8 && m<=15)
				dd= Coil_Bit_Read(&bf[3], m-8);
              addr= PARA_IO[i].addr_do -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DO_BARE[bytes], bitno, dd);
           }
          break; 
        case I8056:  // 16 DO channel
        case I8057:
          ldata= GetDIOData32(slot);
		  memcpy(bf, (char *)&ldata, 4);
          for(m=0; m<chnl_out; m++)
           {
			  if(m<8)
				dd= Coil_Bit_Read(&bf[0], m);
			  else
				dd= Coil_Bit_Read(&bf[1], m-8);
              addr= PARA_IO[i].addr_do -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DO_BARE[bytes], bitno, dd);
           }
          break;
        case I8064:  // 8 DO channel
        case I8065:  // 8 DO channel
        case I8066:  // 8 DO channel
        case I8068:  // 8 DO channel
        case I8069:  // 8 DO channel
        case I8060:  // 6 channel DO
          ldata= GetDIOData32(slot);
		  memcpy(bf, (char *)&ldata, 4);
          for(m=0; m<chnl_out; m++)
           {
 			  dd= Coil_Bit_Read(&bf[0], m);
              addr= PARA_IO[i].addr_do -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DO_BARE[bytes], bitno, dd);
           }
          break;
        case I8054:  // 8 DI and 8 DO
        case I8055:  
          ldata= GetDIOData32(slot);
		  memcpy(bf, (char *)&ldata, 4);
          for(m=0; m<chnl_in; m++)
           {
 			  dd= Coil_Bit_Read(&bf[0], m);
              addr= PARA_IO[i].addr_di -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DI_BARE[bytes], bitno, dd);
           }
          for(m=0; m<chnl_out; m++)
           {
 			  dd= Coil_Bit_Read(&bf[1], m);
              addr= PARA_IO[i].addr_do -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DO_BARE[bytes], bitno, dd);
           }
          break; 
        case I8063:  // 4 DI and 4 DO
          ldata= GetDIOData32(slot);
		  memcpy(bf, (char *)&ldata, 4);
          for(m=0; m<chnl_in; m++)
           {
 			  dd= Coil_Bit_Read(&bf[0], m);
              addr= PARA_IO[i].addr_di -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DI_BARE[bytes], bitno, dd);
           }
          for(m=0; m<chnl_out; m++)
           {
 			  dd= Coil_Bit_Read(&bf[0], m+4);
              addr= PARA_IO[i].addr_do -1 +m;
			  bytes= addr/8;
			  bitno= addr%8;
  			  Coil_Bit_Write(&Coil.DO_BARE[bytes], bitno, dd);
           }
          break; 
      }
   }

   return;

}
/*...........................................................................*/
/* Check output Queue and set DO or AO                                       */
/*...........................................................................*/
int local_check_qbuff02(void)
{
   int  i, slot, bytes, bitno, module, dd, rec, chnl, gain;
   int  s1, s2, addr_1, word_1;
   AODO_OUTPUT  output02;
   float  fl;
   unsigned short data;
   unsigned long ldata;
   unsigned char  bf[10];
   CString  msg;

   rec= 0;
   if( que_FIFO_read((char *)QBUFF10, (char *)&output02, QUEUE_SIZE,
         AODO_RD_INDEX,  AODO_WT_INDEX, rec, QUEUE_MAX_CASE) != 0)  // it has no output data
      return(-1);  

// it has output data;
   que_FIFO_del(QUEUE_MAX_CASE, &AODO_RD_INDEX, &AODO_WT_INDEX);


   addr_1= output02.addr;
// find Slot No. and Module No.
   if(output02.type == DO_TYPE)
    {
	   for(i=0, slot=0, chnl=-1; i<SLOT_MAX_CASE; i++)
	   {
		   if(PARA_IO[i].mod_no == 0) continue;  // empty slot
		   module= PARA_IO[i].mod_no;
           if(module==I8041 || module==I8056 || module==I8057 || module==I8060 ||
			  module==I8064 || module==I8065 || module==I8066 || module==I8068 ||
			  module==I8069 ||
			  module==I8042 || module==I8054 || module==I8055 || module==I8063 )
		   {
				addr_1= output02.addr;
				s1= PARA_IO[i].addr_do -1;

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