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PSDsoft Express Version 8.50
Output of PSD Fitter
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PROJECT : fapiao DATE : 03/24/2006
DEVICE : uPSD3254A TIME : 10:31:08
FIT OPTION : Keep Current
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==== Pin Layout for U (80-Pin TQFP) Package Type ====
-----------------------------
| |
pd2 |1 ] pd2 adio4 [41| Address Bus a4/Data Port d4, ad4
USBINIT |2 ] p3_3 p3_5 [42| Flash_busy
pd1 |3 ] pd1 adio5 [43| Address Bus a5/Data Port d5, ad5
ale |4 ] pd0 p3_6 [44| SDA
Go_paper |5 ] pc7 adio6 [45| Address Bus a6/Data Port d6, ad6
tdo, TDO |6 ] pc6/TDO p3_7 [46| COMCS1
tdi, TDI |7 ] pc5/TDI adio7 [47| Address Bus a7/Data Port d7, ad7
USB_minus |8 ] USBm Xtal1 [48| Xtal1
pc4 |9 ] pc4/TERR Xtal2 [49| Xtal2
USB_plus |10] USBp VCC [50|
|11] N/C adio8 [51| Address Bus a8, a8
|12] VCC p1_0 [52| PrintEN
|13] GND adio9 [53| Address Bus a9, a9
pc3 |14] pc3/TSTAT p1_1 [54| PrintCS
pc2 |15] pc2 adio10 [55| Address Bus a10, a10
tck, TCK |16] pc1/TCK p1_2 [56| RXD1
|17] N/C adio11 [57| Address Bus a11, a11
p4_7 |18] p4_7 p1_3 [58| TXD1
MOSI |19] p4_6 p1_4 [59| ICRST1
tms, TMS |20] pc0/TMS p1_5 [60| ICCTR1
PeriphDIR |21] pa7 p1_6 [61| ICRST2
KEYCS |22] pa6 cntl0 [62| _wr
MISO |23] p4_5 cntl2 [63| _psen
VCC_O |24] pa5 p1_7 [64| ICCTR2
SCL |25] p4_4 cntl1 [65| _rd
MotoOn |26] pa4 pb7 [66| USBHOSTCS
PCO4 |27] p4_3 pb6 [67| PeriphCE
Fast_paper_feed |28] pa3 Reset_In [68| _Reset_In
|29] GND GND [69|
PCO3 |30] p4_2 Vref [70| VREF
PCO2 |31] p4_1 N/C [71|
Black_mark_out |32] pa2 pb5 [72| LCDDI
PCO1 |33] p4_0 pb4 [73| LCDWR
R_pulse_out |34] pa1 pb3 [74| LCDE
T_pulse_out |35] pa0 p3_0 [75| RXD0
ad0, Address Bus a0/Data Port d0 |36] adio0 pb2 [76| LCDCS3
ad1, Address Bus a1/Data Port d1 |37] adio1 p3_1 [77| TXT0
ad2, Address Bus a2/Data Port d2 |38] adio2 pb1 [78| LCDCS2
ad3, Address Bus a3/Data Port d3 |39] adio3 p3_2 [79| PWRINIT
ICINT |40] p3_4 pb0 [80| LCDCS1
| |
-----------------------------
==== Global Configuration ====
Data Bus : 8-Bit
Address/Data Mode : Multiplexed
ALE/AS Signal : Active High
Control Signals : /WR, /RD, /PSEN
Main PSD flash memory will reside in this space at power-up : Program space
Secondary PSD flash memory will reside in this space at power-up : Program space
Enable Chip-Select Input(/CSI) : OFF
Standby Voltage Input (PC2) : OFF
Standby-on Indicator (PC4) : OFF
RDY/Busy function (PC3) : OFF
Load Micro-Cell on : edge
Security Protection : ON
==== DataBus_IMC access information ====
CSIOP
Location Address Offset Register Name Signals
--------------------------------------------------------
===== Resource Usage Summary =====
Total Product Terms Used: 48
Device Resources used / total
------------------------------------------------
Port A: (pins 35 34 32 28 26 24 22 21)
I/O Pins : 8 / 8
GP I/O or Address Out : 6
Peripheral I/O : 0
Logic Inputs : 0
Address Latch Inputs : 0
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
Combinatorial Outputs : 2
Registered Outputs : 0
Other Information
Microcells : 3 / 8
Micro-Cells AB :
Buried Microcells : 1
Output Microcells : 2
Product Terms : 7 / 24
Control Product Terms : 3 / 34
Allocated locally : 2
Allocated to other port : 1
Port B: (pins 80 78 76 74 73 72 67 66)
I/O Pins : 8 / 8
GP I/O or Address Out : 0
Logic Inputs : 0
Address Latch Inputs : 0
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
Combinatorial Outputs : 8
Registered Outputs : 0
Other Information
Microcells : 8 / 8
Micro-Cells AB :
Buried Microcells : 0
Output Microcells : 0
Micro-Cells BC :
Buried Microcells : 0
Output Microcells : 8
Product Terms : 13 / 32
Control Product Terms : 9 / 34
Allocated locally : 8
Allocated to other port : 1
Port C: (pins 20 16 15 14 9 7 6 5)
I/O Pins : 8 / 8
GP I/O or Address Out : 4
Logic Inputs : 0
Address Latch Inputs : 0
PT Dependent Latch Inputs : 0
PT Dependent Register Inputs : 0
JTAG signals : 4
Standby Voltage Input : 0
Rdy/Bsy signal : 0
Standby On Indicator : 0
Combinatorial Outputs : 0
Registered Outputs : 0
Other Information
Microcells : 8 / 8
Micro-Cells BC :
Buried Microcells : 8
Output Microcells : 0
Product Terms : 13 / 32
Control Product Terms : 1 / 34
Allocated locally : 0
Allocated to other port : 1
Port D: (pins 4 3 1)
I/O Pins : 3 / 3
GP I/O or Address Out : 2
Logic Inputs : 0
Chip-Select Input : 0
Clock Input : 0
Control Signal Input : 1
Fast Decoding Outputs : 0
Other Information
Product Terms : 0 / 3
Control Product Terms : 0 / 3
==== OMC Resource Assignment ====
Resources PT User
Used Allocation Name
---------------------------------------------------------
Micro-Cell AB :
Micro-Cells 0 Yes rs0_0 => Combinatorial
Micro-Cells 6 - KEYCS (mcellab6) => Combinatorial
Micro-Cells 7 Yes PeriphDIR (mcellab7) => Combinatorial
Micro-Cell BC :
Micro-Cells 0 - LCDCS1 (mcellbc0) => Combinatorial
Micro-Cells 1 - LCDCS2 (mcellbc1) => Combinatorial
Micro-Cells 2 - LCDCS3 (mcellbc2) => Combinatorial
Micro-Cells 3 - LCDE (mcellbc3) => Combinatorial
Micro-Cells 4 - LCDWR (mcellbc4) => Combinatorial
Micro-Cells 5 - LCDDI (mcellbc5) => Combinatorial
Micro-Cells 6 Yes PeriphCE (mcellbc6) => Combinatorial
Micro-Cells 7 - USBHOSTCS (mcellbc7) => Combinatorial
External Chip Select :
========= Equations =========
DPLD EQUATIONS :
=======================
fs0 = !pdn & !pgr2 & !pgr1 & !pgr0 & a15;
fs1 = !pdn & !pgr2 & !pgr1 & pgr0 & a15;
fs2 = !pdn & !pgr2 & pgr1 & !pgr0 & a15;
fs3 = !pdn & !pgr2 & pgr1 & pgr0 & a15;
fs4 = !pdn & pgr2 & !pgr1 & !pgr0 & a15;
fs5 = !pdn & pgr2 & !pgr1 & pgr0 & a15;
fs6 = !pdn & pgr2 & pgr1 & !pgr0 & a15;
fs7 = !pdn & pgr2 & pgr1 & pgr0 & a15;
csboot0 = !pdn & !a15 & !a14 & !a13;
csboot1 = !pdn & !a15 & !a14 & a13;
csboot2 = !pdn & !a15 & a14 & !a13;
csboot3 = !pdn & !a15 & a14 & a13;
csiop = !pdn & !a15 & !a14 & !a13 & !a12 & !a11 & !a10 & a9 & !a8;
rs0 = rs0_0.FB;
jtagsel = !_reset;
PORTA EQUATIONS :
=======================
!rs0_0 = (a15)
# (!a14 & !a13 & !a12 & !a11 & !a10 & !a9)
# (!a14 & !a13 & !a12 & !a11 & !a10 & !a8)
# (pdn);
!KEYCS = !_rd & a15 & a14 & a13 & !a12 & !a11 & !a10 & !a9 & !a8 & !a7 & !a6 & !a5 & !a4 & a3 & a2 & !a1 & !a0;
KEYCS.OE = 1;
!PeriphDIR = (!_rd & a15 & !a14)
# (!_rd & a15 & !a13)
# (!_rd & a15 & !a12 & !a11)
# (!_rd & a15 & !a12 & !a10 & !a9 & !a8 & !a7 & !a6 & !a5 & !a4 & !a3 & !a2 & !a1 & !a0);
PeriphDIR.OE = 1;
PORTB EQUATIONS :
=======================
!LCDCS1 = a15 & !a14 & a13 & !a12 & !a11 & a10;
LCDCS1.OE = 1;
!LCDCS2 = a15 & !a14 & a13 & !a12 & a11 & !a0;
LCDCS2.OE = 1;
!LCDCS3 = a15 & !a14 & a13 & a12 & !a11 & !a10;
LCDCS3.OE = 1;
LCDE = (!_rd & a15 & !a14 & a13)
# (!_wr & a15 & !a14 & a13);
LCDE.OE = 1;
LCDWR = a15 & !a14 & a13 & a9;
LCDWR.OE = 1;
LCDDI = a15 & !a14 & a13 & a8;
LCDDI.OE = 1;
!PeriphCE = (!_rd & a15 & !a14)
# (!_rd & a15 & !a13)
# (!_rd & a15 & !a12 & !a11)
# (!_rd & a15 & !a12 & !a10 & !a9 & !a8 & !a7 & !a6 & !a5 & !a4 & !a3 & !a2 & !a1 & !a0)
# (!_wr);
PeriphCE.OE = 1;
!USBHOSTCS = (!_rd & a15 & a14 & a13 & !a12 & !a11 & !a10 & !a9 & !a8 & !a7 & !a6 & !a5 & !a4 & !a3 & !a2 & !a1 & !a0)
# (!_wr & a15 & a14 & a13 & !a12 & !a10 & !a9 & !a8 & !a7 & !a6 & !a5 & !a4 & !a3 & !a2 & !a1 & !a0);
USBHOSTCS.OE = 1;
PORTC EQUATIONS :
=======================
PORTD EQUATIONS :
=======================
--- End ---
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