mcbsp.asm

一个滤波器和一个音效处理程序 TI 的CCS 编译器编程。

	 LD     #0, DP                 ; reset data-page pointer
     	 STM    #0, CLKMD              ; software setting of DSP clock
      	 STM    #0, CLKMD              ; (to divider mode before setting)
     	 STM    #0x1007, CLKMD         ; set C5402 DSP clock to 40MHz
     	
 ******* Configure C5402 System Registers *******
      STM   #0x2000, SWWSR          ; 2 wait cycle for IO space &
                                    ; 0 wait cycle for data&prog spaces 
      STM   #0x0000,BSCR            ; set wait states for bank switch:
                                    ; 64k mem bank, extra 0 cycle between
                                    ; consecutive prog/data read     
      STM   #0x1800,ST0             ; ST0 at default setting
      STM   #0x2900,ST1             ; ST1 at default setting(note:INTX=1)
      STM   #0x00A0,PMST            ; MC mode & OVLY=1, vectors at 0080h
      ******* Set up Timer Control Registers *******     
      STM   #0x0010, TCR            ; stop on-chip timer0  
      STM   #0x0010, TCR1           ; stop on-chip timer1 
                                    ; Timer0 is used as main loop timer
      STM   #2499, PRD              ; timer0 rate=CPUCLK/1/(PRD+1)
                                    ;            =40M/2500=16KHz
                                  
 ******* Initialize McBSP0 Registers *******
      STM   SPCR1,  McBSP0_SPSA     ; register subaddr of SPCR1
      STM   #4020h, McBSP0_SPSD     ; McBSP0 recv = left-justify
                                    ; RINT generated by frame sync                                    
      STM   SPCR2,  McBSP0_SPSA     ; register subaddr for SPCR2
                                    ; XINT generated by frame sync
      STM   #0020h, McBSP0_SPSD     ; McBSP0 Tx = FREE(clock stops 
                                    ; to run after SW breakpoint)                              

      STM   RCR1,   McBSP0_SPSA     ; register subaddr of RCR1
      STM   #0040h, McBSP0_SPSD     ; recv frame1 Dlength = 16 bits 
      STM   RCR2,   McBSP0_SPSA     ; register subaddr of RCR2
      STM   #0041h, McBSP0_SPSD     ; recv Phase = 1
                                    ; Set frame2 Dlength = 16bits

      STM   XCR1,   McBSP0_SPSA     ; register subaddr of XCR1
      STM   #0040h, McBSP0_SPSD     ; set the same as recv
      STM   XCR2,   McBSP0_SPSA     ; register subaddr of XCR2
      STM   #0041h, McBSP0_SPSD     ; set the same as recv
      
       STM   PCR,    McBSP0_SPSA     ; register subaddress of PCR
      STM   #0000h, McBSP0_SPSD     ; clk and frame from external (slave)
                                    ; FS at pulse-mode(00)