fas466size.h

基于FAS466的SCSI控制器的启动器模式的C源代码。

#include "fas466regs.h"

// Function Prototypes
void InitRegisterSizeArray();


void InitRegisterSizeArray()
{
	int i = 0;

	for (i = 0; i < 0x0FF; i++) {
		RegSizeArray[i] = 0x01;
	}

	RegSizeArray[	SC_Single_Ended_Configuration	] = 0x01;  // 0x24 	 Single Ended Configuration R/W Register
	RegSizeArray[	SC_SCSI_Pad_Configuration2		] = 0x01;  // 0x25   	 SCSI Pad Configuration 0x01;  // 0x2 R/W Register
	RegSizeArray[	SC_Selection_Configuration2		] = 0x02;  // 0x26 	 Selection Configuration 0x01;  // 0x2 Low R/W Register
	RegSizeArray[	SC_Command						] = 0x01;  // 0x20 	 Command R/W Register
	RegSizeArray[	SC_Command_Interrupt_Status		] = 0x01;  // 0x21 	 Command Interrupt Status R/W Register
	RegSizeArray[	SC_Scaling						] = 0x01;  // 0x22 	 Scaling R/W Register
	RegSizeArray[	SC_SCSI_Pad_Configuration1		] = 0x01;  // 0x23 	 SCSI Pad Configuration 0x01;  // 0x1 R/W Register
	RegSizeArray[	SC_Command_Status				] = 0x01;  // 0x04 	 Command Status R Register
	RegSizeArray[	SC_Error_Interrupt_Status		] = 0x01;  // 0x05 	 Error Interrupt Status R/W register
	RegSizeArray[	SC_SCSI_Data					] = 0x02;  // 0x06 	 SCSI Data Low R/W register
	RegSizeArray[	SC_SCSI_Control					] = 0x02;  // 0x08 	 SCSI Control low R/W register
	RegSizeArray[	SC_FIFO							] = 0x01;  // 0x0A 	 FIFO Data R/W register
	RegSizeArray[	SC_FIFO_Count					] = 0x01;  // 0x0B 	 FIFO Count R register
	RegSizeArray[	SC_Block_Size					] = 0x02;  // 0x0C 	 Block Size Low R/W register
	RegSizeArray[	SC_Block_Size_Counter			] = 0x02;  // 0x0E 	 Block Size Counter Low R register
	RegSizeArray[	SC_Almost_Full_FIFO_Threshold	] = 0x01;  // 0x10 	 Almost Full FIFO Threshold R/W register
	RegSizeArray[	SC_Almost_Empty_FIFO_Threshold	] = 0x01;  // 0x11 	 Almost Empty FIFO Threshold R/W register
	RegSizeArray[	SC_Block_Count_Counter			] = 0x02;  // 0x12 	 Block Count Counter Low R/W register
	RegSizeArray[	SC_SCSI_Arbitration_Configuration	] = 0x02;  // 0x14 	 SCSI Arbitration Configuration Low R/W register
	RegSizeArray[	SC_Selection_Configuration1			] = 0x02;  // 0x16 	 Selection Configuration 0x01;  // 0x1 Low R/W register
	RegSizeArray[	SC_SCSI_CDB_Configuration			] = 0x02;  // 0x18 	 SCDI CDB configuration low R/W register
	RegSizeArray[	SC_Selection_Disable				] = 0x01;  // 0x1A 	 Selection RegSizeArray[ble R/W register
	RegSizeArray[	SC_Miscellaneous_Configuration		] = 0x01;  // 0x1B 	 Miscellaneous Configuration R/W register
	RegSizeArray[	SC_Probe_Address					] = 0x01;  // 0x1C 	 Probe Address R/W register
	RegSizeArray[	SC_Probe_Data						] = 0x01;  // 0x1D 	 Probe Data R/W register
	RegSizeArray[	SC_Write_Command_Status_Test		] = 0x01;  // 0x1E 	 Write Command Status Test W Register
	RegSizeArray[	SC_Write_Error_Interrupt_Status_Test] = 0x01;  // 0x1F 	 Write Error Interrupt Status Test W register
	RegSizeArray[ 	SC_Sync_Control						] = 0x01;  // 0x2c
	RegSizeArray[	SC_SCSI_Output_Enable_Control		] = 0x01;  // 0x2d
	RegSizeArray[	MC_Control_Status					] = 0x01;  // 0x40 	control/status r/w
	RegSizeArray[	MC_External_Interupt_Mask			] = 0x01;  // 0x41 	External Interupt Mask r/w
	RegSizeArray[	MC_Address_Pointer					] = 0x02;  // 0x42 	Address Pointer r/w
	RegSizeArray[	MC_Internal_Register_Access			] = 0x01;  // 0x44 	Internal Register Access r/w
	RegSizeArray[	MC_Program_Memory_Byte_Access		] = 0x01;  // 0x45 	Program Memory Byte Access r/w
	RegSizeArray[	MC_Indirect_DMA_Word_Count			] = 0x01;  // 0x46 	Indirect DMA Word Count r/w
	RegSizeArray[	MC_External_Interupt_Status			] = 0x01;  // 0x47 	External Interupt Status r/w
	RegSizeArray[	MC_Interrupt_Parameter				] = 0x01;  // 0x48 	Interupt Parameter r/w
	RegSizeArray[	MC_Firmware_Interrupt				] = 0x01;  // 0x49 	Firmware Interrupt r/w
	RegSizeArray[	MC_Hardware_Semaphore_request_grant	] = 0x01;  // 0x4A 	Hardware Semaphore Request/Grant r/w
	RegSizeArray[	MC_Hardware_Semaphore_Release		] = 0x01;  // 0x4B 	Hardware Semaphore Release w
	RegSizeArray[	MC_Indirect_DMA_Index				] = 0x02;  // 0x4C 	Indirect DMA Index LSB r/w
	//RegSizeArray[	MC_Program_Memory_Word_Access		] = 0x02;  // 0x12E 	Program Memory Word Access r/w
	RegSizeArray[	MC_Mailbox_register0				] = 0x01;  // 0x50 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register1				] = 0x01;  // 0x51 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register2				] = 0x01;  // 0x52 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register3				] = 0x01;  // 0x53 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register4				] = 0x01;  // 0x54 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register5				] = 0x01;  // 0x55 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register6				] = 0x01;  // 0x56 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register7				] = 0x01;  // 0x57 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register8				] = 0x01;  // 0x58 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register9				] = 0x01;  // 0x59 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register10				] = 0x01;  // 0x5A 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register11				] = 0x01;  // 0x5B 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register12				] = 0x01;  // 0x5C 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register13				] = 0x01;  // 0x5D 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register14				] = 0x01;  // 0x5E 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register15				] = 0x01;  // 0x5F 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register16				] = 0x01;  // 0x60 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register17				] = 0x01;  // 0x61 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register18				] = 0x01;  // 0x62 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register19				] = 0x01;  // 0x63 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register20				] = 0x01;  // 0x64 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register21				] = 0x01;  // 0x65 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register22				] = 0x01;  // 0x66 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register23				] = 0x01;  // 0x67 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register24				] = 0x01;  // 0x68 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register25				] = 0x01;  // 0x69 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register26				] = 0x01;  // 0x6A 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register27				] = 0x01;  // 0x6B 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register28				] = 0x01;  // 0x6C 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register29				] = 0x01;  // 0x6D 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register30				] = 0x01;  // 0x6E 	Mailbox Registers r/w
	RegSizeArray[	MC_Mailbox_register31				] = 0x01;  // 0x6F 	Mailbox Registers r/w
	RegSizeArray[	MC_Diagnostic_Test_Register1			] = 0x01;  // 0x70 	Diagnostic Test Registers r/w
	RegSizeArray[	MC_Diagnostic_Test_Register2			] = 0x01;  // 0x71 	Diagnostic Test Registers r/w
	RegSizeArray[	MC_General_Purpose_IO_Congig_Register	] = 0x01;  // 0x72
	RegSizeArray[	DI_Configuration						] = 0x01;  // 0x3C
	RegSizeArray[	DI_Interrupt_Status					] = 0x01;  // 0x3D
	RegSizeArray[	DI_Status							] = 0x01;  // 0x3F
	RegSizeArray[	MP_Chip_Config						] = 0x01;  // 0x00
	RegSizeArray[ 	MP_Module_Reset						] = 0x01;  // 0x33
	RegSizeArray[	MP_Gen_PurposeIO_Config				] = 0x01;  // 0x72
	RegSizeArray[	MP_Version							] = 0x01;  // 0x32
	RegSizeArray[	MP_Mode_Select						] = 0x02;  // 0x34
	RegSizeArray[	MP_uP_Interface_Config				] = 0x02;  // 0x36
	RegSizeArray[	MP_Indirect_Reg_Access_isa			] = 0x01;  // 0x38
	RegSizeArray[	MP_Indirect_Reg_Access_Pointer		] = 0x02;  // 0x39
}