📄 fas466defs.h
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#define SC_Probe_Addr_REQ_ACK_Diff_MSB 0x18
//*****************************************************************************************************************
// SCSI Probe Data Register and Bit Definitions (Sec 6_25) *
//*****************************************************************************************************************
//disa SC_Probe_Data 0x1D // Probe Data R/W register
//*****************************************************************************************************************
// SCSI Write Command Status Test Register and Bit Definitions (Sec 6_26) *
//*****************************************************************************************************************
//disa SC_Write_Command_Status_Test 0x1E // Write Command Status Test W Register
//*****************************************************************************************************************
// SCSI Write Error Interrupt Status Test Register and Bit Definitions (Sec 6_27) *
//*****************************************************************************************************************
//disa SC_Write_Error_Interrupt_Status_Test 0x1F // Write Error Interrupt Status Test W register
//*****************************************************************************************************************
// SCSI Synchronous Strobe Control Register and Bit Definitions *
//*****************************************************************************************************************
//disa SC_Sync_Control 0x2c
#define Channel_One_FIFO_Strobe 0x10
#define Parity_Error_FlipFlop_Strobe 0x8
#define SCST_Offset_Counter_Strobe 0x4
#define Filtered_REQ_ACK 0x3
#define Raw_REQ_ACK 0x2
#define Synchronized_Only_REQ_ACK 0x1
//*****************************************************************************************************************
// SCSI Output Enable Control Register and Bit Definitions *
//*****************************************************************************************************************
//disa SC_SCSI_Output_Enable_Control 0x2d
#define RST_BSY_SEL_Output_Enable 0x8
#define MSG_CD_IO_ATN_Output_Enable 0x4
#define REQ_ACK_Output_Enable 0x2
#define SD15_0_And_SDP1_0_Output_Enable 0x1
//*****************************************************************************************************************
// MicroController Registers and Bit Definitions *
//*****************************************************************************************************************
//disa MC_Control_Status 0x40 //control/status r/w
#define MC_Single_Step_Mode 0x10 //Bit4,Single Step Mode
#define MC_DMA_Busy 0x08 //Bit3,DMA Busy
#define MC_Reserved 0x04 //Bit2,Reserved
#define MC_Microcontroller_State 0x03 //Bit1-0,Microcontroller State
#define MC_Idle 0x00 //Bit1-000h,Idle
#define MC_Running 0x01 //Bit1-001h,Running
#define MC_Reset 0x03 //Bit1-003h, Reset
//disa MC_External_Interupt_Mask 0x41 //External Interupt Mask r/w
#define MC_External_INTK_Interrupt_Mask 0x20 //Bit5,External INT 0xK Interrupt Mask
#define MC_BC_Exception_Interrupt 0x04 //Bit2,BC Exception Interrupt
#define MC_SCSI_Exception_Interrupt 0x02 //Bit1,SCSI Exception Interrupt
#define MC_SCSI_Command_Complete_Interrupt 0x01 //bit0,SCSI Command Complete Interrup
//disaw MC_Address_Pointer 0x42 //Address Pointer r/w
//disa MC_Internal_Register_Access 0x44 //Internal Register Access r/w
//disa MC_Program_Memory_Byte_Access 0x45 //Program Memory Byte Access r/w
//disa MC_Indirect_DMA_Word_Count 0x46 //Indirect DMA Word Count r/w
//disa MC_External_Interupt_Status 0x47 //External Interupt Status r/w
#define MC_Microcontroller_Interrupt_Pending_rw 0x20 //Bit5,Microcontroller Interrupt Pending(r/w)
//#define MC_BC_Exception_Interrupt 0x04 //Bit2,BC Exception Interrupt
//#define MC_SCSI_Exception_Interrupt 0x02 //Bit1,SCSI Exception Interrupt
#define MC_SCSI_Commnand_Complete_Interrupt 0x01 //Bit0,SCSI Command Complete Iterrupt
//disa MC_Interrupt_Parameter 0x48 //Interupt Parameter r/w
//disa MC_Firmware_Interrupt 0x49 //Firmware Interrupt r/w
//disa MC_Hardware_Semaphore_request_grant 0x4A //Hardware Semaphore Request/Grant r/w
#define MC_Hardware_Semaphore3_Granted 0x04 //Bit2,Hardware Semaphore 0x3 Granted
#define MC_Hardware_Semaphore2_Granted 0x02 //Bit1,Hardware Semaphore 0x2 Granted
#define MC_Hardware_Semaphore1_Granted 0x01 //Bit0,Hardware Semaphore 0x1 Granted
//disa MC_Hardware_Semaphore_Release 0x4B //Hardware Semaphore Release w
#define MC_Hardware_Semaphore3_Release 0x04 //Bit2,Hardware Semaphore 0x3 Release
#define MC_Hardware_Semaphore2_Release 0x02 //Bit1,Hardware Semaphore 0x2 Release
#define MC_Hardware_Semaphore1_Release 0x00 //Bit0,Hardware Semaphore 0x1 Release
//disaw MC_Indirect_DMA_Index 0x4C //Indirect DMA Index LSB r/w
////disaw MC_Program_Memory_Word_Access 0x12E //Program Memory Word Access r/w
//disa MC_Mailbox_register0 0x50 //Mailbox Registers r/w
//disa MC_Mailbox_register1 0x51 //Mailbox Registers r/w
//disa MC_Mailbox_register2 0x52 //Mailbox Registers r/w
//disa MC_Mailbox_register3 0x53 //Mailbox Registers r/w
//disa MC_Mailbox_register4 0x54 //Mailbox Registers r/w
//disa MC_Mailbox_register5 0x55 //Mailbox Registers r/w
//disa MC_Mailbox_register6 0x56 //Mailbox Registers r/w
//disa MC_Mailbox_register7 0x57 //Mailbox Registers r/w
//disa MC_Mailbox_register8 0x58 //Mailbox Registers r/w
//disa MC_Mailbox_register9 0x59 //Mailbox Registers r/w
//disa MC_Mailbox_register10 0x5A //Mailbox Registers r/w
//disa MC_Mailbox_register11 0x5B //Mailbox Registers r/w
//disa MC_Mailbox_register12 0x5C //Mailbox Registers r/w
//disa MC_Mailbox_register13 0x5D //Mailbox Registers r/w
//disa MC_Mailbox_register14 0x5E //Mailbox Registers r/w
//disa MC_Mailbox_register15 0x5F //Mailbox Registers r/w
//disa MC_Mailbox_register16 0x60 //Mailbox Registers r/w
//disa MC_Mailbox_register17 0x61 //Mailbox Registers r/w
//disa MC_Mailbox_register18 0x62 //Mailbox Registers r/w
//disa MC_Mailbox_register19 0x63 //Mailbox Registers r/w
//disa MC_Mailbox_register20 0x64 //Mailbox Registers r/w
//disa MC_Mailbox_register21 0x65 //Mailbox Registers r/w
//disa MC_Mailbox_register22 0x66 //Mailbox Registers r/w
//disa MC_Mailbox_register23 0x67 //Mailbox Registers r/w
//disa MC_Mailbox_register24 0x68 //Mailbox Registers r/w
//disa MC_Mailbox_register25 0x69 //Mailbox Registers r/w
//disa MC_Mailbox_register26 0x6A //Mailbox Registers r/w
//disa MC_Mailbox_register27 0x6B //Mailbox Registers r/w
//disa MC_Mailbox_register28 0x6C //Mailbox Registers r/w
//disa MC_Mailbox_register29 0x6D //Mailbox Registers r/w
//disa MC_Mailbox_register30 0x6E //Mailbox Registers r/w
//disa MC_Mailbox_register31 0x6F //Mailbox Registers r/w
#define MC_Mailbox_Data 0xFF //Bit7-0,Mailbox 0xn Data
//disa MC_Diagnostic_Test_Register1 0x70 //Diagnostic Test Registers r/w
//disa MC_Diagnostic_Test_Register2 0x71 //Diagnostic Test Registers r/w
//disa MC_General_Purpose_IO_Congig_Register 0x72
#define Enable_GP0_Interrupt 0x8
#define Enable_Last_Block_Output 0x4
#define SC_FCNT_Mask 0x7f
#define SC_CTRL_PhaseMask 0x8700
#define SC_CTRL_MsgInPhase 0x8700
#define SC_CTRL_MsgOutPhase 0x8600
#define SC_CTRL_StatusPhase 0x8300
#define SC_CTRL_CmdPhase 0x8200
#define SC_CTRL_DataInPhase 0x8100
#define SC_CTRL_DataOutPhase 0x8000
#define SC_CTRL_BusFreePhase 0x0000
#define SC_SEL_SyncOffset31 0x1f00
#define SC_SEL_SyncOffset30 0x1e00
#define SC_SEL_SyncOffset28 0x1c00
#define SC_SEL_SyncOffset24 0x1800
#define SC_SEL_SyncOffset16 0x1000
#define SC_SEL_SyncOffset15 0x0f00
#define SC_SEL_SyncOffset14 0x0e00
#define SC_SEL_SyncOffset12 0x0c00
#define SC_SEL_SyncOffset08 0x0800
#define SC_SEL_SyncOffset07 0x0700
//*****************************************************************************************************************
// DMA Interface Registers and Bit Definitions *
//*****************************************************************************************************************
//disa DI_Configuration 0x3C
#define DMA_Enable 0x80
#define DMA_Parity_Generation 0x4
#define DMA_Parity_Check 0x2
#define DMA_Interface_Module_Reset 0x1
//disa DI_Interrupt_Status 0x3D
#define DMA_Data_Parity_Error 1
//disa DI_Status 0x3F
#define Data_In_FIFO 0x80
#define DREQ 0x40
#define DACK 0x20
//#define DBOE 0x10
//#define PAUSE 0x8
#define FF_FE 0x4
#define AE_AF 0x2
#define Last_Block 0x1
//*****************************************************************************************************************
// DMA Controller Registers and Bit Definitions *
//*****************************************************************************************************************
//disa MP_Chip_Config 0x00
//disa MP_Module_Reset 0x33
//disa MP_Gen_PurposeIO_Config 0x72
//disa MP_Version 0x32
//disaw MP_Mode_Select 0x34
//disaw MP_uP_Interface_Config 0x36
//disa MP_Indirect_Reg_Access_isa 0x38
//disaw MP_Indirect_Reg_Access_Pointer 0x39
//#define Enable_Last_Block_Output 0x4
// interrupts
//disa Int0 0xff2e
//disa Int1 0xff2e
// bits
#define Int1_Mask 0x20
#define Int0_Mask 0x10
//*****************************************************************************************************************
// DMA Controller Registers and Bit Definitions *
//*****************************************************************************************************************
#define EnableDMA 0x80
//#define Pause 0x40
#define Load_Counter 0x20
#define Send_Data 0x1
//dreg DC_Configuration #0
//dreg DC_Status #3
//dregw DC_Transfer_Counter #1
//dregw DC_RamData #4
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