fas466defs.h

基于FAS466的SCSI控制器的启动器模式的C源代码。

	#define 	SC_Mul_LUN_Disabl_Command_Received		 0x10	// Bits 6-41h, Multiple LUN //disabled Command 								//received
	#define 	SC_No_Disabl_mess_stop_Command_Rec		 0x00	// Bits 6-40h, No //disabled message or stopped 
															// command received
	#define 	SC_Sequence_Step						 0x0F	// Bits 3-0, Sequence Step


	//*****************************************************************************************************************
	//						SCSI Error Interrupt Status Register and Bit Definitions (Sec 6_8)                       *
	//*****************************************************************************************************************

	//disa	SC_Error_Interrupt_Status				 0x05 	// Error Interrupt Status R/W register
	#define 	SC_Buffer_Controller_Error				 0x80	// Bit 7, Buffer Controller Error
	#define 	SC_SCSI_Bus_Reset						 0x40	// Bit 6 SCSI Bus Reset
	#define 	SC_SCSI_Bus_Type_Change					 0x20	// Bit 5 SCSI Bus Type Change
	#define 	SC_Synchronous_Offset_Error				 0x10	// Bit 4 Synchronous Offset Error
	#define 	SC_SCSI_DMA_Disabled					 0x08	// Bit 3 SCSI DMA //disabled
	#define 	SC_Illegal_Write_Error					 0x04	// Bit 2 Illegal Write Error
	#define 	SC_Illegal_Command_Error				 0x02	// Bit 1 Illegal Command Error
	#define 	SC_FIFO_Overflow_Underflow_Error		 0x01	// Bit 0 FIFO Overflow/Underflow Error


	//*****************************************************************************************************************
	//						SCSI Data Register and Bit Definitions (Sec 6_9)                                         *
	//*****************************************************************************************************************


	//disaw	SC_SCSI_Data							 0x06 	// SCSI Data Low R/W register
	#define 	SC_SD15_8								 0xFF00	// Bit 15-8, SD15-8
	#define 	SC_SD7_0								 0xFF	// Bit 7-0, SD7-0


	//*****************************************************************************************************************
	//						SCSI Control Register and Bit Definitions (Sec 6_10)                                     *
	//*****************************************************************************************************************

	//disaw	SC_SCSI_Control							 0x08 	// SCSI Control low R/W register
	#define 	SC_BSY									 0x8000	// Bit 15, BSY
	#define 	SC_SEL									 0x4000	// Bit 14, SEL
	#define 	SC_ATN									 0x2000	// Bit 13, ATN
	#define 	SC_REQ									 0x1000	// Bit 12, REQ
	#define 	SC_ACK									 0x800	// Bit 11, ACK
	#define 	SC_MSG									 0x400	// Bit 10, MSG
	#define 	SC_CD									 0x200	// Bit 9, C/D
	#define 	SC_IO									 0x100	// Bit 8, I/O
	#define 	SC_RST									 0x80	// Bit 7, RST
	#define 	SC_EARB									 0x40	// Bit 6, EARB Read only bit
	#define 	SC_EBSY									 0x20	// Bit 5, EBSY Read only bit
	#define 	SC_ESEL									 0x10	// Bit 4, ESEL Read only bit
	#define 	SC_EIGS									 0x8	// Bit 3, EIGS Read only bit
	#define 	SC_ETGS									 0x4	// Bit 2, ETGS Read only bit
	#define 	SC_SDP1									 0x2	// Bit 1, SDP1 
	#define 	SC_SDP0									 0x1	// Bit 0, SDP0
	
  
	//*****************************************************************************************************************
	//						SCSI FIFO Data Register and Bit Definitions (Sec 6_11)                                   *
	//*****************************************************************************************************************
	 
	//disa	SC_FIFO									 0x0A 	// FIFO Data R/W register



	//*****************************************************************************************************************
	//						SCSI FIFO Count Register and Bit Definitions (Sec 6_12)                                  *
	//*****************************************************************************************************************

	//disa	SC_FIFO_Count							 0x0B 	// FIFO Count R register


	//*****************************************************************************************************************
	//						SCSI Block Size Register and Bit Definitions (Sec 6_13)                                  *
	//*****************************************************************************************************************

	//disaw	SC_Block_Size							 0x0C 	// Block Size Low R/W register
	#define 	SC_Preload_Reload_Block_Size			 0xFFFF	// Bit 15-0, Preload/Reload Block Size in Bytes


	//*****************************************************************************************************************
	//						SCSI Block Size Counter Register and Bit Definitions (Sec 6_14)                          *
	//*****************************************************************************************************************

	//disaw	SC_Block_Size_Counter					 0x0E 	// Block Size Counter Low R register
	#define 	SC_Current_Block_Count_in_Bytes			 0xFFFF	// Bit 15-0, Current Block Count in Bytes

	//*****************************************************************************************************************
	//						SCSI Almost Full FIFO Threshold Register and Bit Definitions (Sec 6_15)                  *
	//*****************************************************************************************************************

	//disa	SC_Almost_Full_FIFO_Threshold			 0x10 	// Almost Full FIFO Threshold R/W register
	#define 	SC_Almost_Full_Threshold				 0xFF	// Bit 7-0, Almost Full Threshold


	//*****************************************************************************************************************
	//						SCSI Almost Empty FIFO Threshold Register and Bit Definitions (Sec 6_16)                 *
	//*****************************************************************************************************************


	//disa	SC_Almost_Empty_FIFO_Threshold			 0x11 	// Almost Empty FIFO Threshold R/W register
	#define 	SC_Almost_Empty_Threshold				 0xFF	// Almost Empty Threshold


	//*****************************************************************************************************************
	//						SCSI Block Count Counter Register and Bit Definitions (Sec 6_18)                         *
	//*****************************************************************************************************************

	//disaw	SC_Block_Count_Counter					 0x12 	// Block Count Counter Low R/W register


	//*****************************************************************************************************************
	//						SCSI Arbitration Configuration Register and Bit Definitions (Sec 6_19)                   *
	//*****************************************************************************************************************

	//disaw	SC_SCSI_Arbitration_Configuration		 0x14 	// SCSI Arbitration Configuration Low R/W register
	#define 	SC_SCSI_Test_Mode_Enable				 0x8000	// Bit 15, SCSI Test Mode Enable
	#define 	SC_SCAM_Selection_Enable				 0x800	// Bit 11, SCAM Selection Enable
	#define 	SC_SCAM_Slow_Selection_Response			 0x400	// Bit 10, SCAM Slow Selection Response

	#define 	SC_Selection_Reselection_Timeout		 0x300	// Bit 9-8, Selection/Reselection Timeout
	#define 	SC_3ms_Timeout							 0x100	// Bit 9-81h, 3 ms
	#define 	SC_250ms_Timeout						 0x0	// Bit 9-80h, 250 ms

	#define 	SC_SCSI_Parity_Configuration			 0xC0	// Bit 7-6, SCSI Parity Configuration
	#define 	SC_En_Parity_Check_Test_Mode			 0x80	// Bit 7-62h, Enable parity checking and test mode
	#define 	SC_Enable_Parity_Checking				 0x40	// Bit 7-61h, Enable Parity Checking
	#define 	SC_Disable_Parity_Checking				 0x00	// Bit 7-60h, //disable Parity Checking

	#define 	SC_Asynchronous_Delay_States			 0x30	// Bit 5-4, Asynchronous Delay States
	#define 	SC_Arbitration_ID0						 0x0	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID1						 0x1	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID2						 0x2	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID3						 0x3	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID4						 0x4	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID5						 0x5	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID6						 0x6	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID7						 0x7	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID8						 0x8	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID9						 0x9	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID10						 0xA	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID11						 0xB	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID12						 0xC	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID13						 0xD	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID14						 0xE	// Bit 3-0, Arbitration ID
	#define 	SC_Arbitration_ID15						 0xF	// Bit 3-0, Arbitration ID


	//*****************************************************************************************************************
	//						SCSI Selection Configuration 0x1 Register and Bit Definitions (Sec 6_20)                  *
	//*****************************************************************************************************************

	//disaw	SC_Selection_Configuration1				 0x16 	// Selection Configuration 0x1 Low R/W register
	#define 	SC_Synchronous_Offset					 0x3F00	// Bit 13-8, Synchronous Offset

	#define 	SC_Transfer_Configuration				 0xF0	// Bit 7-4, Transfer Configuration
	#define 	SC_Wide_Fast40_Sync_25ns				 0x90	// Bit 7-49h, Wide Fast40 sync Width16, 25ns
	#define 	SC_Narrow_Fast40_Sync_25ns				 0x80	// Bit 7-48h, Narrow Fast40 sync Width8, 25ns
	#define 	SC_Wide_Ultra_Sync_50ns					 0x70	// Bit 7-47h, Wide Ultra sync Width16, 50ns
	#define 	SC_Narrow_Ultra_Sync_50ns				 0x60	// Bit 7-46h, Narrow Ultra sync Width8, 50ns
	#define 	SC_Wide_Fast_Sync_100ns					 0x50	// Bit 7-45h, Wide Fast Syns Width16, 100ns
	#define 	SC_Narrow_Fast_Sync_100ns				 0x40	// Bit 7-44h, Narrow Fast Sync Width8, 100ns
	#define 	SC_Wide_Sync_200ns						 0x30	// Bit 7-43h, Wide Sync Width16, 200ns
	#define 	SC_Narrow_Sync_200ns					 0x20	// Bit 7-42h, Narrow Sync Width8, 200ns
	#define 	SC_Wide_Async							 0x10	// Bit 7-41h, Wide Async Width16
	#define 	SC_Narrow_Async							 0x00	// Bit 7-40h, Narrow Async Width8

	#define 	SC_Selection_ID0						 0x0	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID1						 0x1	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID2						 0x2	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID3						 0x3	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID4						 0x4	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID5						 0x5	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID6						 0x6	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID7						 0x7	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID8						 0x8	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID9						 0x9	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID10						 0xA	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID11						 0xB	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID12						 0xC	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID13						 0xD	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID14						 0xE	// Bit 3-0, Selection ID	
	#define 	SC_Selection_ID15						 0xF	// Bit 3-0, Selection ID	


	//*****************************************************************************************************************
	//						SCSI CDB Configuration Register and Bit Definitions (Sec 6_22)                           *
	//*****************************************************************************************************************

	//disaw	SC_SCSI_CDB_Configuration				 0x18 	// SCDI CDB configuration low R/W register
	#define 	SC_Translate_Six_Byte_CDB				 0x100	// Bit 8, Translate Six Byte CDB
	#define 	SC_Stop_if_Read_Command					 0x80	// Bit 7, Stop if Read Command
	#define 	SC_Stop_if_Write_Command				 0x40	// Bit 6, Stop if Write Command
	#define 	SC_Stop_if_Inquiry_Command				 0x20	// Bit 5, Stop if Inquiry Command
	#define 	SC_Stop_if_Request_Sense_Command		 0x10	// Bit 4, Stop if Request Sense Command
	#define 	SC_Stop_if_Test_Unit_Ready_Command		 0x08	// Bit 3, Stop if Test Unit Ready Command
	#define 	SC_Stop_if_Multiple_LUN_ID_Message		 0x04	// Bit 2, Stop if Multiple LUN ID Message
	#define 	SC_Disable_Tagged_Commands				 0x02	// Bit 1, //disable Tagged Commands
	#define 	SC_Disable_TTD_Message					 0x01	// Bit 0, //disable TTD Message


	//*****************************************************************************************************************
	//						SCSI Selection //disable Register and Bit Definitions (Sec 6_17)                           *
	//*****************************************************************************************************************

	//disa	SC_Selection_Disable					 0x1A 	// Selection //disable R/W register
	#define 	SC_Selection_Disable_Request			 0x0	// Bit 0, Selection //disable Request


	//*****************************************************************************************************************
	//						SCSI Miscellaneous Config Register and Bit Definitions (Sec 6_23)                        *
	//*****************************************************************************************************************

	//disa	SC_Miscellaneous_Configuration			 0x1B 	// Miscellaneous Configuration R/W register
	#define 	SC_Pad_Test								 0x10	// Bit 4, Pad Test
	#define 	SC_SCSI_DMA_disable						 0x08	// Bit 3, SCSI DMA //disable
	#define 	SC_SCSI_ATN_Abort_Enable				 0x04	// Bit 2, SCSI ATN Abort Enable
	#define 	SC_Block_Count_32_Enable				 0x02	// Bit 1, Block Count 32 Enable
	#define 	SC_SCSI_RST_Interrupt_Mask				 0x01	// Bit 0, SCSI RST Interrupt Mask


	//*****************************************************************************************************************
	//						SCSI Probe Address Register and Bit Definitions (Sec 6_24)                               *
	//*****************************************************************************************************************

	//disa	SC_Probe_Address						 0x1C 	// Probe Address R/W register
	#define 	SC_Probe_Addr_REQ_ACK_Diff_LSB			 0x17	// Bit 7-0, Probe Address