📄 fas466defs.h
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//*****************************************************************************************************************
// fas466 defines
//
//*****************************************************************************************************************
// SCSI Single Ended Configuration Register and Bit Definitions (Section 6_6) *
//*****************************************************************************************************************
#define IsaBaseAdr 0x250
#define FAS_REG_ADDR 0x7
#define FAS_REG_DATA 0x6
#define RAM_ADDR_LO 0x1
#define RAM_ADDR_HI 0x2
#define RAM_DATA_LO 0x4
#define RAM_DATA_HI 0x5
#define EVAL_STATUS 0x3
#define EVAL_CONFIG 0x0
#define set 1
#define reset 0
//disa SC_Single_Ended_Configuration 0x24 // Single Ended Configuration R/W Register
#define SC_RST_BSY_SEL_SE_ConstDrive_Mode 0x00 // Bits 7-6 RST, BSY, SEL Single Ended Constant Drive Mode
#define SC_RST_BSY_SEL_SE_OpenDrain_Mode 0x40 // Bits 7-6 RST, BSY, SEL Single Ended Open Drain Mode
#define SC_RST_BSY_SEL_SE_Active_Neg_Mode 0xC0 // Bits 7-6 RST, BSY, SEL Single Ended Active Negation Mode
#define SC_ATN_MSG_CD_IO_SE_ConstDrive_Mode 0x00 // Bit 5-4 ATN, MSG, CD, IO Single Ended Constant Drive Mode
#define SC_ATN_MSG_CD_IO_SE_OpenDrain_Mode 0x10 // Bit 5-4 ATN, MSG, CD, IO Single Ended Open Drain Mode
#define SC_ATN_MSG_CD_IO_SE_Active_Neg_Mode 0x30 // Bit 5-4 ATN, MSG, CD, IO Single Ended Active Negation Mode
#define SC_REQ_ACK_SE_ConstDrive_Mode 0x00 // Bit 3-2 REQ, ACK Single Ended Constant Drive Mode
#define SC_REQ_ACK_SE_OpenDrain_Mode 0x04 // Bit 3-2 REQ, ACK Single Ended Open Drain Mode
#define SC_REQ_ACK_SE_Active_Neg_Mode 0x0C // Bit 3-2 REQ, ACK Single Ended Active Negation Mode
#define SC_SD_SE_ConstDrive_Mode 0x00 // Bit 1-0 SD(0-15, P0, P1) Mode
#define SC_SD_SE_OpenDrain_Mode 0x01 // Bit 1-0 SD(0-15, P0, P1) Mode
#define SC_SD_SE_Active_Neg_Mode 0x03 // Bit 1-0 SD(0-15, P0, P1) Mode
//*****************************************************************************************************************
// SCSI Pad Configuration0x2 Register and Bit Definitions (Sec 6_5_2) *
//*****************************************************************************************************************
//disa SC_SCSI_Pad_Configuration2 0x25 // SCSI Pad Configuration 0x2 R/W Register
#define SC_SCSI_PAD_Slew_Rate_Control 0x00 // Bits 4-3 SCSI PAD Slew Rate Control
#define SC_//disable_LVD 0x04 // Bit 2 //disable LVD receiver when in SCSI
// Xmit mode
#define SC_Data_Analog_Filter_Enable 0x02 // Bit 1 Data Analog Filter Enalbe
#define SC_REQ_ACK_Analog_Filter_Enable 0x01 // Bit 0 REQ/ACK Analog Filter Enable
//*****************************************************************************************************************
// SCSI Selection Configuration0x2 Register and Bit Definitions (Sec 6_21) *
//*****************************************************************************************************************
//disaw SC_Selection_Configuration2 0x26 // Selection Configuration 0x2 Low R/W Register
//#define SC_REQ_ACK_Digital_Filter_Config 0xF00 // Bits 11-8 REQ/ACK Digital Filter Delay
#define SC_Digital_Filter_Disabled 0x000 // Bits 11-80h, Digital Filter //disabled
#define SC_0_5_1_Clock_Periods 0x100 // Bits 11-81h, 0_5 to 1 Clock periods(160MHz)
#define SC_1_5_2_Clock_Periods 0x200 // Bits 11-82h, 1_5 to 2 Clock periods (160MHz)
#define SC_2_5_3_Clock_Periods 0x300 // Bits 11-83h, 2_5 to 3 Clock periods (160MHz)
#define SC_3_5_4_Clock_Periods 0x400 // Bits 11-84h, 3_5 to 4 Clock periods (160MHz)
#define SC_4_5_5_Clock_Periods 0x500 // Bits 11-85h, 4_5 to 5 Clock periods (160MHz)
#define SC_6_5_7_Clock_Periods 0x700 // Bits 11-87h, 6_5 to 7 Clock perio (160MHz
#define SC_7_5_8_Clock_Periods 0x800 // Bits 11-88h, 7_5 to 8 Clock periods(160MHz)
//#define SC_REQ_ACK_Assertion_Config 0xC0 // Bits 7-6 REQ/ACK Assertion Delay
#define SC_0_Clock_Assertion_Delay 0x00 // Bits 7-600h, No Clock Assertion Delay (80MHz)
#define SC_0_5_Clock_Assertion_Delay 0x40 // Bits 7-61h, 1/2 Clock Assertion Delay (80MHz)
#define SC_1_Clock_Assertion_Delay 0x80 // Bits 7-62h, 1 Clock Assertion Delay (80MHz)
#define SC_1_5_Clock_Assertion_Delay 0xC0 // Bits 7-63h, 1 1/2 Clock Assertion Delay (80MHz)
//#define SC_REQ_ACK_Deassertion_Config 0x30 // Bits 5-4 REQ/ACK Deassertion Delay
#define SC_0_Clock_Deassertion_Delay 0x00 // Bits 5-40h, No Clock Deasssertion Delay (80MHz)
#define SC_0_5_Clock_Deassertion_Delay 0x10 // Bits 5-41h, 1/2 Clock Deassertion Delay (80MHz)
#define SC_1_Clock_Deassertion_Delay 0x20 // Bits 5-42h, 1 Clock Deassertion Delay (80MHz)
#define SC_1_5_Clock_Deassertion_Delay 0x30 // Bits 5-43h, 1 1/2 Clock Deassertion Delay (80MHz)
//#define SC_Synchronous_Transfer_Period 0x07 // Bits 2-0 Synchronous Transfer Period (Delay states)
#define SC_375ns_275ns_225ns_112_5ns 0x07 // Bits 2-07h, Sync375ns, FastSync275ns // UltraSync225ns, Fast-40112_5ns
#define SC_350ns_250ns_200ns_100ns 0x06 // Bits 2-06h, Sync350ns, FastSync250ns,
// UltraSync200ns, Fast-40100ns
#define SC_325ns_225ns_175ns_87_5ns 0x05 // Bits 2-05h, Sync325ns, FastSync225ns,
// UltraSync175ns, Fast-4087_5ns
#define SC_300ns_200ns_150ns_75ns 0x04 // Bits 2-04h, Sync300ns, FastSync200ns,
// UltraSync150ns, Fast-4075ns
#define SC_275ns_175ns_125ns_62_5ns 0x03 // Bits 2-03h, Sync275ns, FastSync175ns,
// UltraSync125ns, Fast-4062_5ns
#define SC_250ns_150ns_100ns_50ns 0x02 // Bits 2-02h, Sync250ns, FastSync150ns,
// UltraSync100ns, Fast-4050ns
#define SC_225ns_125ns_75ns_37_5ns 0x01 // Bits 2-01h, Sync225ns, FastSync125ns,
// UltraSync75ns, Fast-4037_5ns
#define SC_200ns_100ns_50ns_25ns 0x00 // Bits 2-00h, Sync200ns, FastSync100ns,
// UltraSync50ns, Fast-4025ns
//*****************************************************************************************************************
// SCSI Command Register and Bit Definitions (Sec 6_2) *
//*****************************************************************************************************************
//disa SC_Command 0x20 // Command R/W Register
#define SC_CMD_Reselect_Sequence 0x4B // SCSI Command Reselect Sequence
#define SC_CMD_Select_Without_ATN_Seq 0x48 // SCSi Command Select Without ATN Sequence
#define SC_CMD_Select1_With_ATN_Seq 0x40 // SCSI Command Select With No message
#define SC_CMD_Select2_With_ATN_Seq 0x41 // SCSI Command Select With 1 message
#define SC_CMD_Select3_With_ATN_Seq 0x42 // SCSI Command Select With 2 messages
#define SC_CMD_Select4_With_ATN_Seq 0x43 // SCSI Command Select With 3 messages
#define SC_CMD_Select5_With_ATN_Seq 0x44 // SCSI Command Select With 4 messages
#define SC_CMD_Select6_With_ATN_Seq 0x45 // SCSI Command Select With 5 messages
#define SC_CMD_Select7_With_ATN_Seq 0x46 // SCSI Command Select With 6 messages
#define SC_CMD_Select8_With_ATN_Seq 0x47 // SCSI Command Select With 7 messages
#define SC_CMD_Select_With_ATN_Stop_Seq 0x49 // SCSI Command Select With ATn and Stop Sequence
#define SC_CMD_Enable_Selection_Reslection 0x4F // SCSI Command Enable Selection Reselection
#define SC_CMD_Arbitrate_WithoutID 0x4D // SCSI Command Arbitrate Without ID
#define SC_CMD_Arbitrate_WithID 0x4C // SCSI Command Arbitrate With ID
#define SC_CMD_Disconnect 0x27 // SCSI Command Disconnect
#define SC_CMD_Disconnect_With_Message 0x2E // SCSI Command Disconncet With Message
#define SC_CMD_Disconnect_With_Save_Pointers 0x2F // SCSI Command Disconnect with Save pointers and message
#define SC_CMD_Disconnect_Sequence 0x23 // SCSI Command Disconncect Sequence
#define SC_CMD_Send_Data_Non_DMA 0x22 // SCSI Command Send Data Non-DMA
#define SC_CMD_Send_Data_DMA 0xA2 // SCSI Command Send Data DMA
#define SC_CMD_Receive_Data_Non_DMA 0x2A // SCSI Command Receive Data Non-DMA
#define SC_CMD_Receive_Data_DMA 0xAA // SCSI Command Receive Data DMA
#define SC_CMD_Target_Cmd_Compl_Seq_FIFO_Disc 0x24 // SCSI Command Target Cmd Complete Seq FiFo Disconnect
#define SC_CMD_Target_Cmd_Compl_Seq_GOOD_Disc 0x2C // SCSI Command Target Cmd Complete Seq GOOD Disconnect
#define SC_CMD_Target_Cmd_Compl_Seq_FIFO_NoDisc 0x25 // SCSI Command Targer Cmd Complete Seq FIFO NO Disconnect
#define SC_CMD_Send_Message 0x20 // SCSI Command Send message
#define SC_CMD_Receive_Message 0x28 // SCSI Command Receive message
#define SC_CMD_Receive_Command_Seq 0x2B // SCSI Command Receive Command Sequence
#define SC_CMD_Receive_Command 0x29 // SCSI Command Receive Command
#define SC_CMD_Send_Status 0x21 // SCSI Command Send Status
#define SC_CMD_Xfer_Information_Non_DMA 0x10 // SCSI Command Transfer Information Non-DMA
#define SC_CMD_Xfer_Information_DMA 0x90 // SCSI Command Transfer Information DMA
#define SC_CMD_Xfer_Pad 0x98 // SCSI Command Transfer Pad
#define SC_CMD_Initiator_Cmd_Complete_Seq 0x11 // SCSI Command Initiator Command Complete Sequence
#define SC_CMD_Message_Accepted 0x12 // SCSI Command Message Accepted
#define SC_CMD_Assert_ATN 0x1A // SCSI Command Assert ATN
#define SC_CMD_Deassert_ATN 0x1B // SCSI Command Deassert ATN
#define SC_CMD_NOP 0x00 // SCSI Command NOP
#define SC_CMD_Flush_FIFO 0x01 // SCSI Command Flush FIFO
#define SC_CMD_Drain_FIFO 0x81 // SCSI Command Drain FIFO
#define SC_CMD_Target_Test_Mode 0x71 // SCSI Command Target Test Mode
#define SC_CMD_Initiator_Test_Mode 0x70 // SCSI Command Initiator Test MOde
#define SC_CMD_Sequencer_Interrupt_Test 0x02 // SCSI Command Sequencer Interrrupt Test
//*****************************************************************************************************************
// SCSI Command Interrupt Status Register and Bit Definitions (Sec 6_3) *
//*****************************************************************************************************************
//disa SC_Command_Interrupt_Status 0x21 // Command Interrupt Status R/W Register
#define SC_Exception 0x80 // Bit 7 Exception Read Only bit
#define SC_SCSI_Disconnect 0x40 // Bit 6 SCSI Disconnect
#define SC_Bus_Service 0x20 // Bit 5 Bus Service
#define SC_Function_Complete 0x10 // Bit 4 Function Complete
#define SC_Pause_Condition 0x08 // Bit 3 Pause Condition
#define SC_SCSI_Parity_Error 0x04 // Bit 2 SCSI Paritye Error
//#define SC_Bus_Initiated_Event_Status 0x03 // Bits 1-0 Bus-initiated Event Status
#define SC_Bus_Initiated_SCAM_Selection 0x03 // Bits 1-03h, Bus-initiated SCAM Selection
#define SC_Bus_Initiated_Reselection 0x02 // Bits 1-02h, Bus-initiated Reselection
#define SC_Bus_Initiated_Selection 0x01 // Bits 1-01h, Bus-initiated Selection
#define SC_No_Bus_Initiated_Event 0x00 // Bits 1-00h, No Bus-initiated Event
//*****************************************************************************************************************
// SCSI Scaling Register and Bit Definitions (Sec 6_4) *
//*****************************************************************************************************************
//disa SC_Scaling 0x22 // Scaling R/W Register
//#define SC_DIFFSENS_Deglitch_Value 0x0F // Bits 3-0 DIFFSENS Deglitch Value
#define SC_DIFFSENS_Deglitch_Value100_4ms 0x0F // Bits 3-0Fh, 100_4ms Deglitch Value
#define SC_DIFFSENS_Deglitch_Value94_5ms 0x0E // Bits 3-0Eh, 94_5ms Deglitch Value
#define SC_DIFFSENS_Deglitch_Value64_8ms 0x0D // Bits 3-0Dh, 64_8ms Deglitch Value
#define SC_DIFFSENS_Deglitch_Value55ms 0x0C // Bits 3-0Ch, 55ms Deglitch Value
#define SC_DIFFSENS_Deglitch_Value51_6ms 0x0B // Bits 3-0Bh, 51_6ms Deglitch Value
#define SC_DIFFSENS_Deglitch_Value41_7ms 0x0A // Bits 3-0Ah, 41_7ms Deglitch Value
#define SC_DIFFSENS_Deglitch_Value12ms 0x09 // Bits 3-09h, 12ms Deglitch Value
#define SC_DIFFSENS_Deglitch_Value2_05ms 0x08 // Bits 3-08h, 2_05ms Deglitch Value
#define SC_DIFFSENS_Deglitch_Value1_5us 0x07 // Bits 3-07h, 1_5us Deglitch Value
#define SC_DIFFSENS_Deglitch_Value1_3us 0x06 // Bits 3-06h, 1_3us Deglitch Value
#define SC_DIFFSENS_Deglitch_Value1_1us 0x05 // Bits 3-05h, 1_1us Deglitch Value
#define SC_DIFFSENS_Deglitch_Value900ns 0x04 // Bits 3-04h, 900ns Deglitch Value
#define SC_DIFFSENS_Deglitch_Value700ns 0x03 // Bits 3-03h, 700ns Deglitch Value
#define SC_DIFFSENS_Deglitch_Value500ns 0x02 // Bits 3-02h, 500ns Deglitch Value
#define SC_DIFFSENS_Deglitch_Value300ns 0x01 // Bits 3-01h, 300ns Deglitch Value
#define SC_DIFFSENS_Deglitch_Value100ns 0x00 // Bits 3-00h, 100ns Deglitch Value
//*****************************************************************************************************************
// SCSI Pad Configuration 0x1 Register and Bit Definitions (Sec 6_5_1) *
//*****************************************************************************************************************
//disa SC_SCSI_Pad_Configuration1 0x23 // SCSI Pad Configuration 0x1 R/W Register
#define SC_DIFFSENS_Value 0xC0 // Bits 7-6 DIFFSENS Value(Read Only)
#define SC_HVD 0x80 // Bits 7-62h, HVD DIFFSENS Value
#define SC_LVD 0x40 // Bits 7-61h, LVD DIFFSENS Value
#define SC_Single_Ended 0x00 // Bits 7-60h, Single Ended DIFFSENS Value
#define SC_Disable_SCSI_Pad_Drivers 0x10 // Bit 4, //disable SCSI Pad Drivers
#define SC_Pad_Configuration 0x03 // Bits 1-0, Pad Configuration
#define SC_HVD_Pad_Mode 0x02 // Bits 1-02h, HVD Pad Mode
#define SC_LVD_Pad_Mode 0x01 // Bits 1-01h, LVD Pad Mode
#define SC_Single_Ended_Pad_Mode 0x00 // Bits 1-00h, Single Ended Pad Mode
//*****************************************************************************************************************
// SCSI Command Status Register and Bit Definitions (Sec 6_7) *
//*****************************************************************************************************************
//disa SC_Command_Status 0x04 // Command Status R Register
#define SC_Disconnect_privilege 0x80 // Bit 7, Disconnect Privilege
#define SC_CBD_Stop_Status 0x70 // Bits 6-4, CBD Stop Status
#define SC_Read_Command_Received 0x60 // Bits 6-46h, Read Command Received
#define SC_Write_Command_Received 0x50 // Bits 6-45h, Write Command Received
#define SC_Inquiry_Command_Received 0x40 // Bits 6-44h, Inquiry Command Received
#define SC_Test_Unit_Ready_Command_Received 0x30 // Bits 6-43h, Test Unit Ready Command Received
#define SC_Req_Sense_Command_Received 0x20 // Bits 6-42h, Request Sense Command Received
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