boot.s

自己写的

/*
********************************************************
// Copyright (c)2004 Ark Pioneer Microelectronics Ltd.,
// All Rights Reserved
//
// When load from network, routines run start from symbol(__start).
// We set the exception vector address to 0x80000000.
//
// Filename:boot.s
// Version:1.0
// Created:2005.03   By: Brad
********************************************************
*/

#include "mipsreg.h"
#include "cpureg.h"
#include "cache.h"
#include <stackframe.h>
#include <asm.h>

	/* sde-mips compiler define a symbol __start to run start from. */
	.text
	.globl  Exhndlr
	.globl	__start
	.ent	__start



	.extern FlushDCache
	.extern FlushICache
	
	.extern TLB_exception
	.extern XTLB_exception
	.extern Cache_error
#	.extern ExceptionProcess
        .extern SOC_INTHandler	
	.extern main
	.frame 	sp,24,zero
	
__start:
	.set	noat
	.set	noreorder	
	
	/* 
	 *	Normal boot, and we will cover these instructions below.
	 *	Now we run start from 0xa0050000.(makefile defined)
	 */
	nop
	b	boot
	nop

	/* 
	 *	Firstly, we force the exception handlers from 0xa0050200, then copy 
	 *	these instructions from 0xa0050200 to 0xa0000000. Total need copy 
	 *	0x200 BYTEs(between 0x0200 and 0x0400).
	 * 
	 */
	/* offset 0x200 */	
	.align 	8	# force next address to multiple of 0x100
	.word	0
	.align	8	# 0xa0050200
Exhndlr:
	/* Exception handler, TLB miss:	0xa0000000 */
	la	k0, TLB_exception
	jr	k0
	nop

	/* Exception handler, XTLB miss: 0xa0000080 */
	.align	7	# force next address to multiple of 0x080
	la	k0, XTLB_exception
	jr 	k0
	nop

	/* Exception handler, CACHE ERROR: 0xa0000100 */
	.align  7	# force next address to multiple of 0x080
	la	k0, Cache_error		
	jr	k0
	nop

	/* Exception handler, Others: 0xa0000180 */
	/* We should never use registers except k0&k1 before protect.*/
	.align  7	# force next address to multiple of 0x080
#	la	k0,	ExceptionProcess		
#	jr 	k0
        jal 	SOC_INTHandler
	nop

boot:
	/* Enable interrupts, Clear BEV bit */
	mtc0	zero,CP0_CAUSE		# clear s/w interrupts
	nop
	nop
	mfc0	t0, CP0_STATUS
	nop			
	ori	t0, STATUSF_IP4 | ST0_IE
#	ori	t0, STATUSF_IP7 | ST0_IE
	lui	t1, 0xFFBF
	ori	t1, 0xFFFF
	and	t0, t0, t1		/* clear BEV bit */
	nop
	mtc0	t0, CP0_STATUS
	nop

	/* Set sp, pmon will not run correctly */ 
	la	gp, _gp
/*	li	sp, 0xa0080000	*/
	li	sp, 0x80080000		/*brad:local variable accessed through cache*/
	 
#------ Copy exception handlers, Total Size = 0x200(BYTE) ---------------
	li	a0, 0x80		/* data number(WORD width) which need copy */
	la	a1, Exhndlr		/* src address */
	li	a2, 0x00000000		/* dest address */
	li	t0, 0xa0000000		/* no cached L/S */
	or	a1, a1, t0
	or	a2, a2, t0
	li	t0, 0x0
1:
	lw	t1, 0x0(a1)
	addi	a1, a1, 0x4		/* src address add 4 */
	sw	t1, 0x0(a2)
	addi	t0, 0x1			/* counter add 1 */
	bne	t0, a0, 1b
	addi	a2, a2, 0x4		/* delay slot, dest address add 4 */
	nop	
#--------------------------------------------------------------------------

	/*
	 *	After we copy the exception handlers to 0x80000000, we need FLUSH the 
	 *  I-cache and D-cache, so the cpu will know that exception handlers have
	 *	been changed.
	 *
	 */
	jal	FlushDCache
	nop

	jal	FlushICache
	nop
	
#-------init compare int------------------

#        mtc0    zero,CP0_COMPARE
#        nop
#        li      t2,0xffff
#        mtc0    zero,CP0_COUNT
#        mtc0	t2, CP0_COMPARE



	/* Entry user's main */	
	#--- call user's main passing two parameters: main(argc, argv)
	la      t0, main
	li      t1, 0x9fffffff		# we will run cached
	and     t0, t0, t1			
	jalr    t0			
	nop
    
	.end
	.set	reorder