📄 dsk5402_dma_ad50.c
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/*
* Copyright 2003 by Texas Instruments Incorporated.
* All rights reserved. Property of Texas Instruments Incorporated.
* Restricted rights to use, duplicate or disclose this code are
* granted through contract.
*
*/
/* "@(#) DDK 1.11.00.00 11-04-03 (ddk-b13)" */
/*
* ======== dsk5402_dma_ad50.c ========
*/
#include <std.h>
#include <atm.h>
#include <hwi.h>
#include <que.h>
#include <csl.h>
#include <csl_dma.h>
#include <csl_mcbsp.h>
#include <iom.h>
#include <c54xx_dma_mcbsp.h>
#include <dsk5402_dma_ad50.h>
#include <ad50.h>
/*
* Forward declaration of IOM interface functions.
*/
static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams);
static Int mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg);
static Int mdSubmitChan(Ptr chanp, IOM_Packet *packet);
/*
* Public IOM interface table.
*/
IOM_Fxns DSK5402_DMA_AD50_FXNS;
/* CSL config structure for McBsp */
static MCBSP_Config mcbspCfg = {
0x0021, /* Serial Port Control Register 1 */
0x0201, /* Serial Port Control Register 2 */
0x0040, /* Receive Control Register 1 */
0x0000, /* Receive Control Register 2 */
0x0040, /* Transmit Control Register 1 */
0x0000, /* Transmit Control Register 2 */
0x0000, /* Sample Rate Generator Register 1 */
0x0000, /* Sample Rate Generator Register 2 */
0x0000, /* Multichannel Control Register 1 */
0x0000, /* Multichannel Control Register 2 */
0x000c, /* Pin Control Register */
0x0000, /* Receive Channel Enable Register Partition A */
0x0000, /* Receive Channel Enable Register Partition B */
0x0000, /* Transmit Channel Enable Register Partition A */
0x0000 /* Transmit Channel Enable Register Partition B */
};
/* CSL config structure for DMAs */
static DMA_Config dmaRxCfg = {
0x0000, /* Channel Priority (0x0000 or 0x0001) */
0x6045, /* Transfer Mode Control Register (DMMCR) */
0x5000, /* Sync Event and Frame Count Register (DMSFC) */
(DMA_AdrPtr)0x0021,/* Source Address Register (DMSRC) - Numeric */
// (DMA_AdrPtr)0x0041,/* Source Address Register (DMSRC) - Numeric */
NULL, /* Destination Address Register (DMDST) - Symbolic */
0x0000 /* Element Count Register (DMCTR) */
};
static DMA_Config dmaTxCfg = {
0x0000, /* Channel Priority (0x0000 or 0x0001) */
0x6141, /* Transfer Mode Control Register (DMMCR) */
0x6000, /* Sync Event and Frame Count Register (DMSFC) */
NULL, /* Source Address Register (DMSRC) - Symbolic */
(DMA_AdrPtr)0x0023, /* Destination Address Register (DMDST) */
// (DMA_AdrPtr)0x0043, /* Destination Address Register (DMDST) */
0x0000 /* Element Count Register (DMCTR) */
};
/*
* ======== mdBindDev ========
*/
#pragma CODE_SECTION(mdBindDev, ".text:init")
static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams)
{
DSK5402_DMA_AD50_DevParams *params =
(DSK5402_DMA_AD50_DevParams *)devParams;
C54XX_DMA_MCBSP_DevParams genericDevParams;
MCBSP_Handle hMcbsp;
DSK5402_DMA_AD50_DevParams defaultParams =
DSK5402_DMA_AD50_DEVPARAMS_DEFAULT;
// static volatile ioport unsigned port04; /* for CPLD CTRL 2 */
/* use default parameters if none are given */
if (params == NULL) {
params = &defaultParams;
}
/* Check the version number */
if (params->versionId != DSK5402_DMA_AD50_VERSION_1){
/* Unsupported version number */
return(IOM_EBADARGS);
}
/* open the McBSP */
// hMcbsp = MCBSP_open(MCBSP_PORT1, MCBSP_OPEN_RESET); //2005.9.8
hMcbsp = MCBSP_open(MCBSP_PORT0, MCBSP_OPEN_RESET);
if (hMcbsp == INV) {
return (IOM_EBADIO);
}
MCBSP_config(hMcbsp, &mcbspCfg);
/*
* DSK5402 board setup ...
* Select McBSP1 mapped to Audio Codec (CPLD Register)
* and FC bit = 0 (secondary control off)
*/
// port04 &= 0xf5;
/* start the McBSP */
MCBSP_start(hMcbsp, MCBSP_XMIT_START | MCBSP_RCV_START, 0x0);
/* set codec parameters (this will also initialize the codec) */
AD50_setParams(hMcbsp, &(params->ad50) );
MCBSP_close(hMcbsp);
genericDevParams.versionId = C54XX_DMA_MCBSP_VERSION_1;
genericDevParams.rxDmaId = params->rxDmaId;
genericDevParams.txDmaId = params->txDmaId;
genericDevParams.mcbspCfg = &mcbspCfg;
genericDevParams.rxIntrMask = params->rxIntrMask;
genericDevParams.txIntrMask = params->txIntrMask;
return (C54XX_DMA_MCBSP_FXNS.mdBindDev(devp, 1, &genericDevParams));
}
/*
* ======== mdCreateChan ========
*/
static Int mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg)
{
C54XX_DMA_MCBSP_ChanParams genericChanParams;
if (mode == IOM_INPUT) {
genericChanParams.dmaCfg = &dmaRxCfg;
}
else if (mode == IOM_OUTPUT) {
genericChanParams.dmaCfg = &dmaTxCfg;
}
else {
return (IOM_EBADMODE);
}
return (C54XX_DMA_MCBSP_FXNS.mdCreateChan(chanp, devp, name, mode,
&genericChanParams, cbFxn, cbArg));
}
static Int mdSubmitChan(Ptr chanp, IOM_Packet *packet)
{
Int i;
Int result;
MdUns *localBuf;
if (packet->cmd == IOM_WRITE) {
/* Mask off the LSB */
localBuf = packet->addr;
for (i = 0; i < (packet->size / sizeof(MdUns)); i++) {
localBuf[i] = localBuf[i] & 0xFFFE;
}
}
result = (C54XX_DMA_MCBSP_FXNS.mdSubmitChan)(chanp, packet);
return (result);
}
/*
* ======== DSK5402_DMA_AD50_init ========
*/
#pragma CODE_SECTION(DSK5402_DMA_AD50_init, ".text:init")
Void DSK5402_DMA_AD50_init(Void)
{
C54XX_DMA_MCBSP_init();
DSK5402_DMA_AD50_FXNS = C54XX_DMA_MCBSP_FXNS;
DSK5402_DMA_AD50_FXNS.mdBindDev = mdBindDev;
DSK5402_DMA_AD50_FXNS.mdCreateChan = mdCreateChan;
DSK5402_DMA_AD50_FXNS.mdSubmitChan = mdSubmitChan;
}
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