📄 clk.rpt
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Total single-pin Output Enables required: 0
Synthesized logic cells: 13/ 576 ( 2%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 8 5 8 1 0 0 0 0 0 8 8 0 38/0
B: 8 6 7 0 0 0 0 5 0 8 8 0 0 0 2 0 0 0 0 0 0 0 0 0 5 49/0
C: 0 3 0 0 8 2 0 0 8 0 0 0 0 5 0 0 0 1 0 8 0 0 8 0 8 51/0
Total: 8 9 7 0 8 2 0 5 8 8 8 0 0 13 7 8 1 1 0 8 0 0 16 8 13 138/0
Device-Specific Information: e:\tjm\clk.rpt
clk
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
55 - - - -- INPUT G 0 0 0 1 CLK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: e:\tjm\clk.rpt
clk
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
12 - - A -- OUTPUT 0 1 0 0 AD1
18 - - B -- OUTPUT 0 1 0 0 AD2
80 - - C -- OUTPUT 0 1 0 0 AD3
21 - - B -- OUTPUT 0 1 0 0 AD4
27 - - C -- OUTPUT 0 1 0 0 AD5
32 - - C -- OUTPUT 0 1 0 0 AD6
33 - - C -- OUTPUT 0 1 0 0 AD7
89 - - B -- OUTPUT 0 1 0 0 AD8
9 - - A -- OUTPUT 0 1 0 0 AD9
81 - - C -- OUTPUT 0 1 0 0 AD10
10 - - A -- OUTPUT 0 1 0 0 AD11
91 - - B -- OUTPUT 0 1 0 0 AD12
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: e:\tjm\clk.rpt
clk
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - A 16 LCELL s 1 0 1 0 AD1~1
- 1 - C 19 AND2 0 2 0 5 |LPM_ADD_SUB:258|addcore:adder|:63
- 1 - C 22 AND2 0 3 0 5 |LPM_ADD_SUB:365|addcore:adder|:71
- 1 - C 13 AND2 0 2 0 5 |LPM_ADD_SUB:485|addcore:adder|:121
- 2 - C 24 AND2 0 3 0 3 |LPM_ADD_SUB:485|addcore:adder|:129
- 6 - C 24 AND2 0 2 0 1 |LPM_ADD_SUB:485|addcore:adder|:133
- 1 - B 02 AND2 0 3 0 6 |LPM_ADD_SUB:618|addcore:adder|:79
- 3 - B 02 AND2 0 2 0 1 |LPM_ADD_SUB:618|addcore:adder|:83
- 3 - B 01 AND2 0 4 0 2 |LPM_ADD_SUB:618|addcore:adder|:91
- 4 - A 22 OR2 ! 0 2 0 3 |LPM_ADD_SUB:764|addcore:adder|:79
- 2 - A 22 OR2 ! 0 3 0 5 |LPM_ADD_SUB:764|addcore:adder|:87
- 1 - A 22 AND2 0 3 0 3 |LPM_ADD_SUB:764|addcore:adder|:95
- 7 - A 15 AND2 0 2 0 1 |LPM_ADD_SUB:764|addcore:adder|:99
- 4 - C 05 AND2 0 3 0 5 |LPM_ADD_SUB:923|addcore:adder|:87
- 1 - C 05 AND2 0 3 0 3 |LPM_ADD_SUB:923|addcore:adder|:95
- 4 - C 09 AND2 0 3 0 3 |LPM_ADD_SUB:923|addcore:adder|:103
- 7 - C 09 AND2 0 2 0 1 |LPM_ADD_SUB:923|addcore:adder|:107
- 1 - A 14 AND2 0 2 0 3 |LPM_ADD_SUB:1095|addcore:adder|:87
- 3 - A 23 AND2 0 3 0 3 |LPM_ADD_SUB:1095|addcore:adder|:95
- 1 - A 23 AND2 0 3 0 3 |LPM_ADD_SUB:1095|addcore:adder|:103
- 4 - A 13 AND2 0 3 0 3 |LPM_ADD_SUB:1095|addcore:adder|:111
- 7 - A 13 AND2 0 2 0 1 |LPM_ADD_SUB:1095|addcore:adder|:115
- 4 - B 08 AND2 0 2 0 1 |LPM_ADD_SUB:1297|addcore:adder|:103
- 3 - B 10 AND2 0 4 0 3 |LPM_ADD_SUB:1297|addcore:adder|:111
- 2 - B 10 AND2 0 3 0 3 |LPM_ADD_SUB:1297|addcore:adder|:119
- 3 - B 03 AND2 0 3 0 3 |LPM_ADD_SUB:1297|addcore:adder|:127
- 1 - B 03 AND2 0 3 0 3 |LPM_ADD_SUB:1297|addcore:adder|:135
- 4 - B 11 AND2 0 3 0 3 |LPM_ADD_SUB:1297|addcore:adder|:143
- 7 - B 11 AND2 0 2 0 1 |LPM_ADD_SUB:1297|addcore:adder|:147
- 2 - B 14 DFFE + 0 1 1 0 :3
- 4 - C 02 DFFE + 0 2 1 0 :5
- 8 - B 24 DFFE + 0 4 1 0 :7
- 2 - C 19 DFFE + 0 4 1 0 :9
- 7 - C 22 DFFE + 0 4 1 0 :11
- 8 - C 24 DFFE + 0 4 1 0 :13
- 5 - B 01 DFFE + 0 4 1 0 :15
- 3 - A 15 DFFE + 0 4 1 0 :17
- 3 - C 05 DFFE + 0 4 1 0 :19
- 4 - A 14 DFFE + 0 4 1 0 :21
- 2 - B 08 DFFE + 0 4 1 0 :23
- 1 - B 14 DFFE + 0 0 0 1 A (:25)
- 1 - C 02 DFFE + 0 1 0 1 A1 (:73)
- 2 - C 02 DFFE + 0 0 0 2 A0 (:74)
- 1 - B 24 DFFE + 0 3 0 2 A3 (:136)
- 2 - B 24 DFFE + 0 2 0 3 A2 (:137)
- 3 - B 24 DFFE + 0 3 0 3 A1~356 (:138)
- 4 - B 24 DFFE + 0 0 0 4 A0~356 (:139)
- 6 - C 19 DFFE + 0 3 0 2 A4 (:225)
- 7 - C 19 DFFE + 0 3 0 3 A3~435 (:226)
- 8 - C 19 DFFE + 0 2 0 4 A2~435 (:227)
- 4 - C 19 DFFE + 0 2 0 1 A1~435 (:228)
- 5 - C 19 DFFE + 0 0 0 2 A0~435 (:229)
- 3 - C 19 OR2 ! 0 4 0 3 :238
- 5 - C 22 DFFE + 0 3 0 2 A5 (:327)
- 6 - C 22 DFFE + 0 3 0 3 A4~514 (:328)
- 8 - C 22 DFFE + 0 2 0 4 A3~514 (:329)
- 4 - C 22 DFFE + 0 3 0 1 A2~514 (:330)
- 3 - C 22 DFFE + 0 2 0 2 A1~514 (:331)
- 1 - C 17 DFFE + 0 0 0 3 A0~514 (:332)
- 2 - C 22 OR2 ! 0 4 0 4 :342
- 7 - C 24 DFFE + 0 3 0 1 A6 (:442)
- 5 - C 24 DFFE + 0 3 0 2 A5~593 (:443)
- 4 - C 24 DFFE + 0 2 0 3 A4~593 (:444)
- 3 - C 13 DFFE + 0 3 0 3 A3~593 (:445)
- 2 - C 13 DFFE + 0 2 0 4 A2~593 (:446)
- 4 - C 13 DFFE + 0 2 0 1 A1~593 (:447)
- 5 - C 13 DFFE + 0 0 0 2 A0~593 (:448)
- 3 - C 24 OR2 s 0 3 0 2 ~459~1
- 1 - C 24 OR2 ! 0 4 0 6 :459
- 8 - B 01 DFFE + 0 3 0 1 A7 (:570)
- 7 - B 01 DFFE + 0 2 0 2 A6~672 (:571)
- 2 - B 02 DFFE + 0 3 0 2 A5~672 (:572)
- 6 - B 01 DFFE + 0 3 0 5 A4~672 (:573)
- 4 - B 01 DFFE + 0 3 0 5 A3~672 (:574)
- 6 - B 02 DFFE + 0 3 0 1 A2~672 (:575)
- 4 - B 02 DFFE + 0 2 0 2 A1~672 (:576)
- 5 - B 02 DFFE + 0 0 0 3 A0~672 (:577)
- 2 - B 01 OR2 s 0 3 0 3 ~589~1
- 1 - B 01 OR2 ! 0 4 0 6 :589
- 8 - A 15 DFFE + 0 3 0 1 A8 (:711)
- 6 - A 15 DFFE + 0 3 0 2 A7~751 (:712)
- 5 - A 15 DFFE + 0 2 0 3 A6~751 (:713)
- 5 - A 22 DFFE + 0 2 0 4 A5~751 (:714)
- 2 - A 15 DFFE + 0 3 0 4 A4~751 (:715)
- 7 - A 22 DFFE + 0 3 0 1 A3~751 (:716)
- 8 - A 22 DFFE + 0 2 0 2 A2~751 (:717)
- 6 - A 22 DFFE + 0 2 0 1 A1~751 (:718)
- 3 - A 22 DFFE + 0 0 0 2 A0~751 (:719)
- 4 - A 15 OR2 s 0 3 0 3 ~732~1
- 1 - A 15 OR2 ! 0 4 0 6 :732
- 8 - C 09 DFFE + 0 3 0 1 A9 (:865)
- 6 - C 09 DFFE + 0 3 0 2 A8~830 (:866)
- 5 - C 09 DFFE + 0 2 0 3 A7~830 (:867)
- 3 - C 09 DFFE + 0 3 0 3 A6~830 (:868)
- 1 - C 09 DFFE + 0 2 0 3 A5~830 (:869)
- 7 - C 05 DFFE + 0 3 0 2 A4~830 (:870)
- 6 - C 05 DFFE + 0 2 0 3 A3~830 (:871)
- 8 - C 05 DFFE + 0 3 0 1 A2~830 (:872)
- 1 - C 06 DFFE + 0 2 0 2 A1~830 (:873)
- 2 - C 06 DFFE + 0 0 0 3 A0~830 (:874)
- 2 - C 09 OR2 s 0 3 0 2 ~888~1
- 5 - C 05 OR2 s 0 3 0 2 ~888~2
- 2 - C 05 OR2 ! 0 4 0 9 :888
- 8 - A 13 DFFE + 0 3 0 1 A10 (:1032)
- 6 - A 13 DFFE + 0 3 0 2 A9~909 (:1033)
- 5 - A 13 DFFE + 0 2 0 3 A8~909 (:1034)
- 3 - A 13 DFFE + 0 3 0 4 A7~909 (:1035)
- 1 - A 13 DFFE + 0 2 0 3 A6~909 (:1036)
- 6 - A 23 DFFE + 0 3 0 2 A5~909 (:1037)
- 5 - A 23 DFFE + 0 2 0 3 A4~909 (:1038)
- 7 - A 23 DFFE + 0 3 0 2 A3~909 (:1039)
- 8 - A 23 DFFE + 0 2 0 3 A2~909 (:1040)
- 3 - A 14 DFFE + 0 2 0 2 A1~909 (:1041)
- 5 - A 14 DFFE + 0 3 0 4 A0~909 (:1042)
- 2 - A 13 OR2 s 0 3 0 3 ~1057~1
- 4 - A 23 OR2 s 0 3 0 1 ~1057~2
- 2 - A 23 OR2 s 0 4 0 3 ~1057~3
- 2 - A 14 OR2 ! 0 4 0 10 :1057
- 8 - B 11 DFFE + 0 3 0 1 A14 (:1212)
- 6 - B 11 DFFE + 0 3 0 2 A13 (:1213)
- 5 - B 11 DFFE + 0 2 0 3 A12 (:1214)
- 3 - B 11 DFFE + 0 3 0 2 A11 (:1215)
- 1 - B 11 DFFE + 0 2 0 3 A10~988 (:1216)
- 7 - B 03 DFFE + 0 3 0 2 A9~988 (:1217)
- 5 - B 03 DFFE + 0 2 0 3 A8~988 (:1218)
- 6 - B 03 DFFE + 0 3 0 2 A7~988 (:1219)
- 4 - B 03 DFFE + 0 2 0 3 A6~988 (:1220)
- 7 - B 10 DFFE + 0 3 0 2 A5~988 (:1221)
- 6 - B 10 DFFE + 0 2 0 3 A4~988 (:1222)
- 5 - B 10 DFFE + 0 3 0 2 A3~988 (:1223)
- 8 - B 10 DFFE + 0 3 0 3 A2~988 (:1224)
- 8 - B 08 DFFE + 0 1 0 6 A1~988 (:1225)
- 3 - B 08 DFFE + 0 3 0 6 A0~988 (:1226)
- 2 - B 11 OR2 s 0 4 0 3 ~1245~1
- 2 - B 03 OR2 s 0 3 0 1 ~1245~2
- 4 - B 10 OR2 s 0 4 0 1 ~1245~3
- 1 - B 10 OR2 s 0 4 0 3 ~1245~4
- 1 - B 08 OR2 ! 0 4 0 13 :1245
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\tjm\clk.rpt
clk
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 16/ 48( 33%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
B: 2/ 96( 2%) 18/ 48( 37%) 1/ 48( 2%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
C: 2/ 96( 2%) 9/ 48( 18%) 6/ 48( 12%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
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