shiyan.vhd

微机接口实验程序 。。 。。 。。 。。 。。 。。 。。

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;




entity SHIYAN is
 port(

        clk:    in std_logic;   --CHU FA SOURCE CHOOSE     
        WAY1:   in std_logic;   
        WAY2:   in std_logic;
        WAY3:   in std_logic;
        CHUFA:  OUT STD_LOGIC --CHU FA ENABLE
      );
END SHIYAN;       
      

architecture SHIYAN of SHIYAN is
                         begin
                      process (CLK)             
    variable A :integer range 0 to 2 :=0;

                 BEGIN
                      IF A=2 THEN 
                         CHUFA<=WAY3;
                      ELSE
                         IF A=1 THEN
                          CHUFA<=WAY2;
                          ELSIF A=0 THEN
                            CHUFA<=WAY1;
                          END IF;
                       END IF;         
                 
                       IF CLK'event and CLK ='1' THEN  
                           if A=2 THEN
                              A:=0;                              
                           ELSE 
                              IF A=0 THEN
                              A:=A+1;                              
                           ELSIF A=1 THEN
                              A:=A+1;                               
                           end IF;
                            END IF;
                       END IF;
                                            


                END PROCESS;                      
                                                          





 END SHIYAN;