📄 shiyan.rpt
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Project Information e:\tjm\shiyan.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 04/02/2006 20:01:03
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
trade secrets, or maskworks, embodied in any such megafunction design,
net list, support information, device programming or simulation file, or
any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
SHIYAN
** DEVICE SUMMARY **
Chip/ Input Output Bidir LCs
POF Device Pins Pins Pins LCs % Utilized
shiyan EP610ILC-10 4 1 0 5 31 %
User Pins: 4 1 0
Project Information e:\tjm\shiyan.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information e:\tjm\shiyan.rpt
** FILE HIERARCHY **
|lpm_add_sub:87|
|lpm_add_sub:87|addcore:adder|
|lpm_add_sub:87|addcore:adder|addcore:adder0|
|lpm_add_sub:87|altshift:result_ext_latency_ffs|
|lpm_add_sub:87|altshift:carry_ext_latency_ffs|
|lpm_add_sub:87|altshift:oflow_ext_latency_ffs|
|lpm_add_sub:95|
|lpm_add_sub:95|addcore:adder|
|lpm_add_sub:95|addcore:adder|addcore:adder0|
|lpm_add_sub:95|altshift:result_ext_latency_ffs|
|lpm_add_sub:95|altshift:carry_ext_latency_ffs|
|lpm_add_sub:95|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\tjm\shiyan.rpt
shiyan
***** Logic for device 'shiyan' compiled without errors.
Device: EP610ILC-10
Device Options:
Turbo Bit = ON
Security Bit = OFF
R R
E E
S S
E E
R W R
V G c V V A V
E N l C C Y E
D D k C C 1 D
-----------------------_
/ 4 3 2 1 28 27 26 |
| |
RESERVED | 5 25 | RESERVED
| |
RESERVED | 6 24 | RESERVED
| |
RESERVED | 7 23 | RESERVED
| |
RESERVED | 8 EP610ILC-10 22 | RESERVED
| |
RESERVED | 9 21 | RESERVED
| |
RESERVED | 10 20 | RESERVED
| |
N.C. | 11 19 | N.C.
|_ 12 13 14 15 16 17 18 _|
------------------------
C W G G G W R
H A N N N A E
U Y D D D Y S
F 3 2 E
A R
V
E
D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\tjm\shiyan.rpt
shiyan
** RESOURCE USAGE **
Logic Array Block Logic Cells I/O Pins
A: LC1 - LC8 0/ 8( 0%) 0/ 8( 0%)
B: LC9 - LC16 5/ 8( 62%) 1/ 8( 12%)
Total dedicated input pins used: 3/4 ( 75%)
Total I/O pins used: 1/16 ( 6%)
Total logic cells used: 5/16 ( 31%)
Average fan-in: 4.00
Total fan-in: 20
Total input pins required: 4
Total output pins required: 1
Total bidirectional pins required: 0
Total logic cells required: 5
Total flipflops required: 2
Synthesized logic cells: 2/ 16 ( 12%)
Device-Specific Information: e:\tjm\shiyan.rpt
shiyan
** INPUTS **
Fan-In Fan-Out
Pin LC LAB Primitive Code INP FBK OUT FBK Name
27 - - INPUT 0 0 1 1 WAY1
17 - - INPUT 0 0 1 1 WAY2
13 - - INPUT 0 0 1 1 WAY3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\tjm\shiyan.rpt
shiyan
** OUTPUTS **
Fan-In Fan-Out
Pin LC LAB Primitive Code INP FBK OUT FBK Name
12 16 B OUTPUT 3 4 0 0 CHUFA
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\tjm\shiyan.rpt
shiyan
** BURIED LOGIC **
Fan-In Fan-Out
Pin LC LAB Primitive Code INP FBK OUT FBK Name
(4) 9 B DFF + 0 1 1 3 A1 (:7)
(5) 10 B TFF + 0 1 1 3 A0 (:8)
(6) 11 B SOFT s 0 2 1 0 ~63~1~2
(7) 12 B LCELL s 3 2 1 0 ~63~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\tjm\shiyan.rpt
shiyan
** LOGIC CELL INTERCONNECTIONS **
Logic cells placed in LAB 'B'
+--------- LC16 CHUFA
| +------- LC9 A1
| | +----- LC10 A0
| | | +--- LC11 ~63~1~2
| | | | +- LC12 ~63~1
| | | | |
| | | | | Other LABs fed by signals
| | | | | that feed LAB 'B'
LC | | | | |
LC16 -> - - - - - | <-- CHUFA
LC9 -> @ - @ @ @ | <-- A1
LC10 -> @ @ @ @ @ | <-- A0
LC11 -> * - - - - | <-- ~63~1~2
LC12 -> * - - - * | <-- ~63~1
Pin
27 -> @ - - - @ | <-- WAY1
17 -> @ - - - @ | <-- WAY2
13 -> @ - - - @ | <-- WAY3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
@ = The input pin or logic cell feeds the logic cell (or LAB) using direct interconnect.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\tjm\shiyan.rpt
shiyan
** EQUATIONS **
clk : INPUT;
WAY1 : INPUT;
WAY2 : INPUT;
WAY3 : INPUT;
-- Node name is ':8' = 'A0'
-- Equation name is 'A0', location is LC010, type is buried.
A0 = TFF(!A1, GLOBAL( clk), VCC, VCC);
-- Node name is ':7' = 'A1'
-- Equation name is 'A1', location is LC009, type is buried.
A1 = DFF( A0, GLOBAL( clk), VCC, VCC);
-- Node name is 'CHUFA'
-- Equation name is 'CHUFA', location is LC016, type is output.
CHUFA = LCELL( _EQ001);
_EQ001 = A0 & !A1 & !_LC011 & WAY2
# !A0 & !A1 & !_LC011 & WAY1
# !A0 & A1 & WAY3
# A1 & !_LC011 & _LC012;
-- Node name is '~63~1~2'
-- Equation name is '~63~1~2', location is LC011, type is buried.
-- synthesized logic cell
_LC011 = LCELL( _EQ002);
_EQ002 = !A0 & A1;
-- Node name is '~63~1'
-- Equation name is '~63~1', location is LC012, type is buried.
-- synthesized logic cell
_LC012 = LCELL( _EQ003);
_EQ003 = A0 & A1 & _LC012
# !A0 & A1 & WAY3
# A0 & !A1 & WAY2
# !A0 & !A1 & WAY1;
Project Information e:\tjm\shiyan.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'CLASSIC' family
MINIMIZATION = full
SOFT_BUFFER_INSERTION = on
TURBO_BIT = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:01
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,682K
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