📄 chufa1.rpt
字号:
& = Uses single-pin Output Enable
Device-Specific Information: e:\tjm\chufa1.rpt
chufa1
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - A 03 DFFE + 0 0 0 3 A0 (:6)
- 4 - A 06 DFFE + 0 3 0 3 A1 (:7)
- 5 - A 06 DFFE + 0 3 0 3 A2 (:8)
- 2 - A 06 OR2 ! 0 3 0 3 :25
- 1 - A 06 AND2 0 3 0 3 :46
- 3 - A 06 OR2 ! 0 3 0 4 :53
- 7 - A 06 AND2 1 1 0 1 :222
- 6 - A 06 OR2 1 3 0 1 :223
- 8 - A 06 OR2 1 3 1 1 :227
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: e:\tjm\chufa1.rpt
chufa1
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 1/16( 6%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\tjm\chufa1.rpt
chufa1
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 3 clk
Device-Specific Information: e:\tjm\chufa1.rpt
chufa1
** EQUATIONS **
clk : INPUT;
WAY1 : INPUT;
WAY2 : INPUT;
WAY3 : INPUT;
-- Node name is ':6' = 'A0'
-- Equation name is 'A0', location is LC1_A3, type is buried.
A0 = DFFE( A0, GLOBAL(!clk), VCC, VCC, VCC);
-- Node name is ':7' = 'A1'
-- Equation name is 'A1', location is LC4_A6, type is buried.
A1 = DFFE( _EQ001, GLOBAL(!clk), VCC, VCC, VCC);
_EQ001 = A1 & !_LC1_A6 & !_LC2_A6
# !_LC1_A6 & !_LC2_A6 & _LC3_A6;
-- Node name is ':8' = 'A2'
-- Equation name is 'A2', location is LC5_A6, type is buried.
A2 = DFFE( _EQ002, GLOBAL(!clk), VCC, VCC, VCC);
_EQ002 = _LC1_A6 & !_LC2_A6
# A2 & !_LC2_A6 & !_LC3_A6;
-- Node name is 'CHUFA'
-- Equation name is 'CHUFA', type is output
CHUFA = _LC8_A6;
-- Node name is ':25'
-- Equation name is '_LC2_A6', type is buried
!_LC2_A6 = _LC2_A6~NOT;
_LC2_A6~NOT = LCELL( _EQ003);
_EQ003 = !A1
# A2
# A0;
-- Node name is ':46'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ004);
_EQ004 = !A0 & !A1 & !A2;
-- Node name is ':53'
-- Equation name is '_LC3_A6', type is buried
!_LC3_A6 = _LC3_A6~NOT;
_LC3_A6~NOT = LCELL( _EQ005);
_EQ005 = A1
# !A2
# A0;
-- Node name is ':222'
-- Equation name is '_LC7_A6', type is buried
_LC7_A6 = LCELL( _EQ006);
_EQ006 = _LC3_A6 & WAY2;
-- Node name is ':223'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = LCELL( _EQ007);
_EQ007 = !_LC1_A6 & !_LC3_A6 & _LC8_A6
# _LC1_A6 & !_LC3_A6 & WAY1;
-- Node name is ':227'
-- Equation name is '_LC8_A6', type is buried
_LC8_A6 = LCELL( _EQ008);
_EQ008 = !_LC2_A6 & _LC6_A6
# !_LC2_A6 & _LC7_A6
# _LC2_A6 & WAY3;
Project Information e:\tjm\chufa1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:02
Memory Allocated
-----------------
Peak memory allocated during compilation = 17,339K
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