📄 adenable.rpt
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LC22 -> - - - - - - - - - - - - | <-- LED1
LC21 -> - - - - - - - - - - - - | <-- LED2
LC20 -> - - - - - - - - - - - - | <-- LED3
LC13 -> - * - * * - - - - - - - | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node1
LC14 -> - * - * * - - - - - - - | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node2
LC15 -> - * - * * - - - - - - - | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3
LC16 -> - @ @ @ @ - - @ @ @ - - | <-- I0
LC17 -> - @ @ @ @ - @ @ @ @ - - | <-- I1
LC18 -> - @ @ @ @ @ @ @ @ @ @ - | <-- I2
LC19 -> - @ @ @ @ @ @ @ @ @ @ @ | <-- I3
Pin
43 -> - - - - - - - - - - - - | <-- AD1
42 -> - - - - - - - - - - - - | <-- AD2
41 -> - - - - - - - - - - - - | <-- AD3
27 -> - - - - - - - - - - - - | <-- AD4
26 -> - - - - - - - - - - - - | <-- AD5
25 -> - - - - - - - - - - - - | <-- AD6
21 -> - - - - - - - - - - - - | <-- AD7
20 -> - - - - - - - - - - - - | <-- AD8
19 -> - - - - - - - - - - - - | <-- AD9
5 -> - - - - - - - - - - - - | <-- AD10
4 -> - - - - - - - - - - - - | <-- AD11
3 -> - - - - - - - - - - - - | <-- AD12
LC12 -> - - * * * - - * - - - - | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|~245~1
LC11 -> * - - - - - - - - - - - | <-- ~611~1
LC10 -> * - - - - - - - - - - - | <-- ~611~2
LC9 -> * - - - - - - - - - - - | <-- ~611~3
LC8 -> * - - - - - - - - - - - | <-- ~611~4
LC7 -> * - - - - - - - - - - - | <-- ~611~5
LC6 -> * - - - - - - - - - - - | <-- ~611~6
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
@ = The input pin or logic cell feeds the logic cell (or LAB) using direct interconnect.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\tjm\adenable.rpt
adenable
** EQUATIONS **
AD1 : INPUT;
AD2 : INPUT;
AD3 : INPUT;
AD4 : INPUT;
AD5 : INPUT;
AD6 : INPUT;
AD7 : INPUT;
AD8 : INPUT;
AD9 : INPUT;
AD10 : INPUT;
AD11 : INPUT;
AD12 : INPUT;
clk : INPUT;
-- Node name is 'ADOUT' = ':2'
-- Equation name is 'ADOUT', type is output
ADOUT = DFF(!_EQ001, GLOBAL( clk), VCC, VCC);
_EQ001 = !_LC006 & !_LC007 & !_LC008 & !_LC009 & !_LC010 & !_LC011;
-- Node name is ':24' = 'I0'
-- Equation name is 'I0', location is LC016, type is buried.
I0 = TFF( _EQ002, GLOBAL( clk), VCC, VCC);
_EQ002 = I0 & I1 & !I2 & !I3
# I1 & I2 & I3;
-- Node name is ':25' = 'I1'
-- Equation name is 'I1', location is LC017, type is buried.
I1 = TFF( _EQ003, GLOBAL( clk), VCC, VCC);
_EQ003 = I0 & I1 & !I2 & !I3
# I2 & I3;
-- Node name is ':26' = 'I2'
-- Equation name is 'I2', location is LC018, type is buried.
I2 = TFF( I3, GLOBAL( clk), VCC, VCC);
-- Node name is ':27' = 'I3'
-- Equation name is 'I3', location is LC019, type is buried.
I3 = TFF( VCC, GLOBAL( clk), VCC, VCC);
-- Node name is 'LED0' = ':16'
-- Equation name is 'LED0', type is output
LED0 = DFF(!_EQ004, GLOBAL( clk), VCC, VCC);
_EQ004 = I1 & I2 & I3 & !_LC013
# I0 & I1 & !I2 & !I3
# !I1 & !I2 & I3 & !_LC013
# I2 & !I3 & _LC014
# !I2 & I3 & _LC014
# !_LC015;
-- Node name is 'LED1' = ':18'
-- Equation name is 'LED1', type is output
LED1 = DFF(!_EQ005, GLOBAL( clk), VCC, VCC);
_EQ005 = I0 & I1 & !I2 & !I3
# I0 & I2 & !I3 & !_LC012
# I1 & I2 & I3
# I0 & I3 & !_LC012
# !I1 & !I3
# !I1 & !I2;
-- Node name is 'LED2' = ':20'
-- Equation name is 'LED2', type is output
LED2 = DFF(!_EQ006, GLOBAL( clk), VCC, VCC);
_EQ006 = I0 & I1 & I2 & I3 & !_LC012
# I0 & I2 & !I3 & !_LC012 & _LC014
# I0 & !I2 & I3 & !_LC012 & _LC014
# !I0 & I1 & I2 & I3
# I0 & I1 & !I2 & !I3
# !I1 & !I2 & I3 & _LC015
# !I3 & !_LC013
# !_LC013 & !_LC015;
-- Node name is 'LED3' = ':22'
-- Equation name is 'LED3', type is output
LED3 = DFF( _EQ007, GLOBAL( clk), VCC, VCC);
_EQ007 = !I0 & I1 & I2 & I3 & !_LC013 & _LC014
# I0 & !I1 & !I2 & I3 & !_LC012
# I0 & I1 & !I2 & !I3
# I0 & !_LC012 & !_LC013 & _LC014
# !I3 & !_LC013
# !I3 & !_LC015;
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC013', type is buried
_LC013 = LCELL( _EQ008);
_EQ008 = I2 & !I3
# !I2 & I3;
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC014', type is buried
_LC014 = LCELL(!_EQ009);
_EQ009 = I1 & I2 & I3
# !I1 & !I3
# !I1 & !I2;
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC015', type is buried
_LC015 = LCELL( _EQ010);
_EQ010 = !I0 & I1 & I2 & I3
# I0 & !_LC012;
-- Node name is '|LPM_ADD_SUB:107|addcore:adder|addcore:adder0|~245~1' from file "addcore.tdf" line 392, column 42
-- Equation name is '_LC012', type is buried
-- synthesized logic cell
_LC012 = LCELL( _EQ011);
_EQ011 = I1 & I2 & I3;
-- Node name is '~611~1'
-- Equation name is '~611~1', location is LC011, type is buried.
-- synthesized logic cell
_LC011 = LCELL( _EQ012);
_EQ012 = AD7 & I2 & !I3 & _LC013 & _LC014 & !_LC015
# AD10 & I2 & !I3 & _LC013 & !_LC014 & _LC015
# AD12 & I2 & !I3 & !_LC013 & _LC014 & _LC015
# AD3 & I2 & !I3 & _LC013 & !_LC014 & !_LC015
# AD6 & I2 & I3 & _LC013 & _LC014 & !_LC015
# AD9 & I2 & I3 & _LC013 & !_LC014 & _LC015
# AD6 & I3 & _LC013 & _LC014 & !_LC015
# AD9 & I3 & _LC013 & !_LC014 & _LC015;
-- Node name is '~611~2'
-- Equation name is '~611~2', location is LC010, type is buried.
-- synthesized logic cell
_LC010 = LCELL( _EQ013);
_EQ013 = AD5 & I2 & !I3 & !_LC013 & _LC014 & !_LC015
# AD11 & I2 & I3 & !_LC013 & _LC014 & _LC015
# AD11 & I3 & !_LC013 & _LC014 & _LC015
# AD8 & I2 & !I3 & !_LC013 & !_LC014 & _LC015
# AD7 & !I0 & !I3 & _LC013 & _LC014 & !_LC015
# AD10 & !I0 & !I3 & _LC013 & !_LC014 & _LC015
# AD7 & !I1 & !I3 & _LC013 & _LC014 & !_LC015
# AD10 & !I1 & !I3 & _LC013 & !_LC014 & _LC015;
-- Node name is '~611~3'
-- Equation name is '~611~3', location is LC009, type is buried.
-- synthesized logic cell
_LC009 = LCELL( _EQ014);
_EQ014 = AD12 & !I0 & !I3 & !_LC013 & _LC014 & _LC015
# AD12 & !I1 & !I3 & !_LC013 & _LC014 & _LC015
# AD4 & I2 & I3 & !_LC013 & _LC014 & !_LC015
# AD4 & I3 & !_LC013 & _LC014 & !_LC015
# AD3 & !I0 & !I3 & _LC013 & !_LC014 & !_LC015
# AD6 & !I0 & I3 & _LC013 & _LC014 & !_LC015
# AD9 & !I0 & I3 & _LC013 & !_LC014 & _LC015
# AD3 & !I1 & !I3 & _LC013 & !_LC014 & !_LC015;
-- Node name is '~611~4'
-- Equation name is '~611~4', location is LC008, type is buried.
-- synthesized logic cell
_LC008 = LCELL( _EQ015);
_EQ015 = AD6 & !I1 & I3 & _LC013 & _LC014 & !_LC015
# AD9 & !I1 & I3 & _LC013 & !_LC014 & _LC015
# AD5 & !I0 & !I3 & !_LC013 & _LC014 & !_LC015
# AD11 & !I0 & I3 & !_LC013 & _LC014 & _LC015
# AD5 & !I1 & !I3 & !_LC013 & _LC014 & !_LC015
# AD11 & !I1 & I3 & !_LC013 & _LC014 & _LC015
# AD8 & !I0 & !I3 & !_LC013 & !_LC014 & _LC015
# AD8 & !I1 & !I3 & !_LC013 & !_LC014 & _LC015;
-- Node name is '~611~5'
-- Equation name is '~611~5', location is LC007, type is buried.
-- synthesized logic cell
_LC007 = LCELL( _EQ016);
_EQ016 = AD4 & !I0 & I3 & !_LC013 & _LC014 & !_LC015
# AD4 & !I1 & I3 & !_LC013 & _LC014 & !_LC015
# AD2 & I2 & _LC013 & _LC014 & _LC015
# AD2 & I3 & _LC013 & _LC014 & _LC015
# AD2 & !I0 & _LC013 & _LC014 & _LC015
# AD2 & !I1 & _LC013 & _LC014 & _LC015
# AD1 & I0 & I1 & !I2 & !I3
# AD2 & I2 & I3 & !_LC013 & !_LC014;
-- Node name is '~611~6'
-- Equation name is '~611~6', location is LC006, type is buried.
-- synthesized logic cell
_LC006 = LCELL( _EQ017);
_EQ017 = AD2 & I3 & !_LC013 & !_LC014
# AD2 & I2 & I3 & !_LC014 & !_LC015
# AD2 & I3 & !_LC014 & !_LC015
# AD1 & !I3 & !_LC013 & !_LC014 & !_LC015
# AD2 & !I0 & I3 & !_LC013 & !_LC014
# AD2 & !I1 & I3 & !_LC013 & !_LC014
# AD2 & !I0 & I3 & !_LC014 & !_LC015
# AD2 & !I1 & I3 & !_LC014 & !_LC015;
Project Information e:\tjm\adenable.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'CLASSIC' family
MINIMIZATION = full
SOFT_BUFFER_INSERTION = on
TURBO_BIT = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:01
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 4,757K
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