📄 adenable.rpt
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Project Information e:\tjm\adenable.rpt
MAX+plus II Compiler Report File
Version 10.2 07/10/2002
Compiled: 03/28/2006 17:04:34
Copyright (C) 1988-2002 Altera Corporation
Any megafunction design, and related net list (encrypted or decrypted),
support information, device programming or simulation file, and any other
associated documentation or information provided by Altera or a partner
under Altera's Megafunction Partnership Program may be used only to
program PLD devices (but not masked PLD devices) from Altera. Any other
use of such megafunction design, net list, support information, device
programming or simulation file, or any other related documentation or
information is prohibited for any other purpose, including, but not
limited to modification, reverse engineering, de-compiling, or use with
any other silicon devices, unless such use is explicitly licensed under
a separate agreement with Altera or a megafunction partner. Title to
the intellectual property, including patents, copyrights, trademarks,
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any other related documentation or information provided by Altera or a
megafunction partner, remains with Altera, the megafunction partner, or
their respective licensors. No other licenses, including any licenses
needed under any third party's intellectual property, are provided herein.
***** Project compilation was successful
ADENABLE
** DEVICE SUMMARY **
Chip/ Input Output Bidir LCs
POF Device Pins Pins Pins LCs % Utilized
adenable EP910ILC-12 13 5 0 19 79 %
User Pins: 13 5 0
Project Information e:\tjm\adenable.rpt
** AUTO GLOBAL SIGNALS **
INFO: Signal 'clk' chosen for auto global Clock
Project Information e:\tjm\adenable.rpt
** FILE HIERARCHY **
|lpm_add_sub:107|
|lpm_add_sub:107|addcore:adder|
|lpm_add_sub:107|addcore:adder|addcore:adder0|
|lpm_add_sub:107|altshift:result_ext_latency_ffs|
|lpm_add_sub:107|altshift:carry_ext_latency_ffs|
|lpm_add_sub:107|altshift:oflow_ext_latency_ffs|
Device-Specific Information: e:\tjm\adenable.rpt
adenable
***** Logic for device 'adenable' compiled without errors.
Device: EP910ILC-12
Device Options:
Turbo Bit = ON
Security Bit = OFF
R R
E E
S S
E E
R A A A R
V D D D c V V A A A V
E 1 1 1 l C C D D D E
D 0 1 2 k C C 1 2 3 D
-----------------------------------_
/ 6 5 4 3 2 1 44 43 42 41 40 |
RESERVED | 7 39 | N.C.
RESERVED | 8 38 | RESERVED
RESERVED | 9 37 | RESERVED
RESERVED | 10 36 | RESERVED
RESERVED | 11 35 | RESERVED
RESERVED | 12 EP910ILC-12 34 | RESERVED
LED3 | 13 33 | RESERVED
LED2 | 14 32 | RESERVED
LED1 | 15 31 | RESERVED
LED0 | 16 30 | RESERVED
N.C. | 17 29 | RESERVED
|_ 18 19 20 21 22 23 24 25 26 27 28 _|
------------------------------------
A A A A G G G A A A R
D D D D N N N D D D E
O 9 8 7 D D D 6 5 4 S
U E
T R
V
E
D
N.C. = No Connect. This pin has no internal connection to the device.
VCC = Dedicated power pin, which MUST be connected to VCC.
GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.
RESERVED = Unused I/O pin, which MUST be left unconnected.
Device-Specific Information: e:\tjm\adenable.rpt
adenable
** RESOURCE USAGE **
Logic Array Block Logic Cells I/O Pins
A: LC1 - LC12 7/12( 58%) 0/12( 0%)
B: LC13 - LC24 12/12(100%) 5/12( 41%)
Total dedicated input pins used: 12/12 (100%)
Total I/O pins used: 5/24 ( 20%)
Total logic cells used: 19/24 ( 79%)
Average fan-in: 6.94
Total fan-in: 132
Total input pins required: 13
Total output pins required: 5
Total bidirectional pins required: 0
Total logic cells required: 19
Total flipflops required: 9
Synthesized logic cells: 7/ 24 ( 29%)
Device-Specific Information: e:\tjm\adenable.rpt
adenable
** INPUTS **
Fan-In Fan-Out
Pin LC LAB Primitive Code INP FBK OUT FBK Name
43 - - INPUT 0 0 0 2 AD1
42 - - INPUT 0 0 0 2 AD2
41 - - INPUT 0 0 0 2 AD3
27 - - INPUT 0 0 0 2 AD4
26 - - INPUT 0 0 0 2 AD5
25 - - INPUT 0 0 0 3 AD6
21 - - INPUT 0 0 0 2 AD7
20 - - INPUT 0 0 0 2 AD8
19 - - INPUT 0 0 0 3 AD9
5 - - INPUT 0 0 0 2 AD10
4 - - INPUT 0 0 0 2 AD11
3 - - INPUT 0 0 0 2 AD12
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\tjm\adenable.rpt
adenable
** OUTPUTS **
Fan-In Fan-Out
Pin LC LAB Primitive Code INP FBK OUT FBK Name
18 24 B FF + 0 6 0 0 ADOUT
16 23 B FF + 0 7 0 0 LED0
15 22 B FF + 0 5 0 0 LED1
14 21 B FF + 0 8 0 0 LED2
13 20 B FF + 0 8 0 0 LED3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\tjm\adenable.rpt
adenable
** BURIED LOGIC **
Fan-In Fan-Out
Pin LC LAB Primitive Code INP FBK OUT FBK Name
(6) 13 B SOFT 0 2 3 6 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node1
(7) 14 B SOFT 0 3 3 6 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node2
(8) 15 B SOFT 0 5 3 6 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3
(28) 12 A SOFT s 0 3 3 1 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|~245~1
(9) 16 B TFF + 0 3 4 7 I0 (:24)
(10) 17 B TFF + 0 3 4 9 I1 (:25)
(11) 18 B TFF + 0 1 4 11 I2 (:26)
(12) 19 B TFF + 0 0 4 13 I3 (:27)
(29) 11 A SOFT s 6 5 1 0 ~611~1
(30) 10 A SOFT s 5 7 1 0 ~611~2
(31) 9 A SOFT s 5 7 1 0 ~611~3
(32) 8 A SOFT s 5 6 1 0 ~611~4
(33) 7 A SOFT s 3 7 1 0 ~611~5
(34) 6 A SOFT s 2 7 1 0 ~611~6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell
Device-Specific Information: e:\tjm\adenable.rpt
adenable
** LOGIC CELL INTERCONNECTIONS **
Logic cells placed in LAB 'A'
+------------- LC12 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|~245~1
| +----------- LC11 ~611~1
| | +--------- LC10 ~611~2
| | | +------- LC9 ~611~3
| | | | +----- LC8 ~611~4
| | | | | +--- LC7 ~611~5
| | | | | | +- LC6 ~611~6
| | | | | | |
| | | | | | | Other LABs fed by signals
| | | | | | | that feed LAB 'A'
LC | | | | | | |
LC12 -> - - - - - - - | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|~245~1
LC11 -> - - - - - - - | <-- ~611~1
LC10 -> - - - - - - - | <-- ~611~2
LC9 -> - - - - - - - | <-- ~611~3
LC8 -> - - - - - - - | <-- ~611~4
LC7 -> - - - - - - - | <-- ~611~5
LC6 -> - - - - - - - | <-- ~611~6
Pin
43 -> - - - - - @ @ | <-- AD1
42 -> - - - - - @ @ | <-- AD2
41 -> - @ - @ - - - | <-- AD3
27 -> - - - @ - @ - | <-- AD4
26 -> - - @ - @ - - | <-- AD5
25 -> - @ - @ @ - - | <-- AD6
21 -> - @ @ - - - - | <-- AD7
20 -> - - @ - @ - - | <-- AD8
19 -> - @ - @ @ - - | <-- AD9
5 -> - @ @ - - - - | <-- AD10
4 -> - - @ - @ - - | <-- AD11
3 -> - @ - @ - - - | <-- AD12
LC13 -> - * * * * * * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node1
LC14 -> - * * * * * * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node2
LC15 -> - * * * * * * | <-- |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3
LC16 -> - - * * * * * | <-- I0
LC17 -> * - * * * * * | <-- I1
LC18 -> * * * * - * * | <-- I2
LC19 -> * * * * * * * | <-- I3
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
@ = The input pin or logic cell feeds the logic cell (or LAB) using direct interconnect.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\tjm\adenable.rpt
adenable
** LOGIC CELL INTERCONNECTIONS **
Logic cells placed in LAB 'B'
+----------------------- LC24 ADOUT
| +--------------------- LC23 LED0
| | +------------------- LC22 LED1
| | | +----------------- LC21 LED2
| | | | +--------------- LC20 LED3
| | | | | +------------- LC13 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node1
| | | | | | +----------- LC14 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node2
| | | | | | | +--------- LC15 |LPM_ADD_SUB:107|addcore:adder|addcore:adder0|result_node3
| | | | | | | | +------- LC16 I0
| | | | | | | | | +----- LC17 I1
| | | | | | | | | | +--- LC18 I2
| | | | | | | | | | | +- LC19 I3
| | | | | | | | | | | |
| | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | |
LC24 -> - - - - - - - - - - - - | <-- ADOUT
LC23 -> - - - - - - - - - - - - | <-- LED0
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