clk.vhd

微机接口实验程序 。。 。。 。。 。。 。。 。。 。。

-- fen pin

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity CLK is
 port(
       CLK:  in std_logic;    --20mhz 
	   AD1:  out std_logic;   --AD clock    20MHZ
       AD2:  out std_logic;   --AD clock    10MHZ
       AD3:  out std_logic;   --AD CLOCK    5MHZ
       AD4:  out std_logic;   --AD CLOCK    2MHZ
       AD5:  out std_logic;   --AD CLOCK    1MHZ
       AD6:  out std_logic;   --AD CLOCK    500KHZ        
       AD7:  out std_logic;   --AD CLOCK    200KHZ
       AD8:  out std_logic;   --AD CLOCK    100KHZ
       AD9:  out std_logic;   --AD CLOCK    50KHZ
       AD10: out std_logic;   --AD CLOCK    20KHZ
       AD11: out std_logic;   --AD CLOCK    10KHZ
       AD12: OUT std_logic    --AD CLOCK    1KHZ
        );
end CLK;

architecture CLK of CLK is
 
  

  begin
               AD1<=CLK;        --20MHZ
              
             process(CLK)  --10MHZ
               variable A :integer range 0 to 1 :=0;   
               begin 
                if CLK'event and CLK ='1'   THEN
               		if A=1 THEN
                 		AD2<='1';  A:=0;
                	ELSE AD2<='0'; A:=A+1;
               		END IF;
            	END IF;
               END PROCESS;
              
      		process(CLK) --5MHZ
                variable A :integer range 0 to 3 :=0;    
                 begin 
                   if CLK'event and CLK ='1'   THEN
               		if A=3 THEN
                 		AD3<='1';  A:=0;
                	ELSE AD3<='0'; A:=A+1;
               		END IF;
            	END IF;
               END PROCESS;
             
             process(CLK) --2MHZ
               variable A :integer range 0 to 9 :=0;    
               begin 
                if CLK'event and CLK ='1'   THEN
               		if A=9 THEN
                 		AD4<='1';  A:=0;
                	ELSE AD4<='0'; A:=A+1;
               		END IF;
            	END IF;
               END PROCESS;
             
            process(CLK)    --1MHZ
               variable A :integer range 0 to 19 :=0;   
               begin 
                if CLK'event and CLK ='1'   THEN
               		if A=19 THEN
                 		AD5<='1';  A:=0;
                	ELSE AD5<='0'; A:=A+1;
               		END IF;
            	END IF;
               END PROCESS;
               
             process(CLK)    --500KHZ
               variable A :integer range 0 to 39 :=0;  
               begin 
                if CLK'event and CLK ='1'   THEN
               		if A=39 THEN
                 		AD6<='1';  A:=0;
                	ELSE AD6<='0'; A:=A+1;
               		END IF;
            	END IF;
              End process;
    

             process(CLK)    --200KHZ
               variable A :integer range 0 to 99 :=0;    
               begin 
                if CLK'event and CLK ='1'   THEN
               		if A=99 THEN
                 		AD7<='1';  A:=0;
                	ELSE AD7<='0'; A:=A+1;
               		END IF;
            	END IF;
              End process;
  


             process(CLK)    --100KHZ
               variable A :integer range 0 to 199 :=0;   
               begin 
                if CLK'event and CLK ='1'   THEN
               		if A=199 THEN
                 		AD8<='1';  A:=0;
                	ELSE AD8<='0'; A:=A+1;
               		END IF;
            	END IF;
              End process;



             process(CLK)    --50KHZ
               variable A :integer range 0 to 399 :=0;   
               begin 
                if CLK'event and CLK ='1'   THEN
               		if A=399 THEN
                 		AD9<='1';  A:=0;
                	ELSE AD9<='0'; A:=A+1;
               		END IF;
            	END IF;
              End process;



              process(CLK)    --20KHZ
               variable A :integer range 0 to 999 :=0;    
                begin 
                 if CLK'event and CLK ='1'   THEN
               		if A=999 THEN
                 		AD10<='1';  A:=0;
                	ELSE AD10<='0'; A:=A+1;
               		END IF;
            	END IF;
              End process;

              process(CLK)    --10KHZ
               variable A :integer range 0 to 2000 :=0;   
               begin 
                if CLK'event and CLK ='1'   THEN
               		if A=2000 THEN
                 		AD11<='1';  A:=0;
                	ELSE AD11<='0'; A:=A+1;
               		END IF;
            	END IF;
              End process;

              process(CLK)    --1KHZ
               variable A :integer range 0 to 20000 :=0;    
               begin 
                if CLK'event and CLK ='1'   THEN
               		if A=20000 THEN
                 		AD12<='1';  A:=0;
                	ELSE AD12<='0'; A:=A+1;
               		END IF;
            	END IF;
              End process;





end CLK;