pm5337_core_xc_masu.tcl

用于EOS芯片的驱动程序, 供参考 参考

  
  ##############################################
  #### 2. Specify G2i byte location 	    ####
  ##############################################
  # Define the number of STM1 needs to be configure
  # mode 1 - STM1#1 to STM1#4 are configured
  # mode 2 - STM1#1 to STM1#8 are configured
  # mode 3 - STM1#1 to STM1#12 are configured
  # mode 4 - STM1#1 to STM1#16 are configured    
  
  if {$mode == 1} {
    set max_STM1 0x3
  } elseif {$mode == 2} {
    set max_STM1 0x7
  } elseif {$mode == 3} {
    set max_STM1 0xB
  } elseif {$mode == 4} {
    set max_STM1 0xF
  }
    
  # In this example, the ingress and egress G2i locations are set to 
  # the same location for all ingress sources.    
  
  set value [expr [expr $g2i_row << 24]|[expr $g2i_col << 16]|[expr $g2i_row << 8]|[expr $g2i_col << 0]]   
  
  # Set ingress G2i location
  admwr $devID 0x2003 $value ;# G2i position 1 and 2
  admwr $devID 0x2004 $value ;# G2i position 3 and 4
  
  # Set egress G2i location
  admwr $devID 0x2005 $value  
  
  # Set EGG2IPOSSEL to 0 for all 48 paths
  # Registers 0x2780 ~ 0x27BF: LOSU Insertion Selection
  # The address A [5:2] bits indicate the STS-3/STM-1 number, which 
  # will be accessed (0000 for the STS-3/STM-1 #1).
  # The address A [1:0] bits indicate the STS-1/STM-0 number, which 
  # will be accessed (00 for the STS-1/STM-0 #1. 11 is reserved).
  
  for {set stm1 0x0} {$stm1 <= $max_STM1} {incr stm1 0x1} {
    for {set stm0 0x0} {$stm0 <= 0x2} {incr stm0 0x1} {        
             
      set addr [expr 0x2780 + [expr $stm1 << 2]|[expr $stm0 << 0]]
      admwrb $devID $addr 9 0

    }
  }
      
  #################################################################
  #### 3. Configuring the FSINS[1:0] bit to enable AU3 to AU4  ####
  ####    conversion       				       ####
  #################################################################
  
  if {$payload == "AU4/TU11" || $payload == "AU4/TU12" || $payload == "AU4/TU2"} {

    # Performing AU3 to AU4 conversion by setting FSINS[1:0] to 10b
    for {set stm1 0x0} {$stm1 <= $max_STM1} {incr stm1 0x1} {
      for {set stm0 0x0} {$stm0 <= 0x2} {incr stm0 0x1} {        
             
        # Defining CM1 register address offset for link 1 and write 
        # settings
        set addr_CM1 [expr 0x2780 + [expr $stm1 << 2]|[expr $stm0 << 0]]                
        admwrb $devID $addr_CM1 6 1 
        admwrb $devID $addr_CM1 5 0 
                
      }
    }    
  } else { 
    # Disable AU3 to AU4 conversion by setting FSINS[1:0] to 00b
    for {set stm1 0x0} {$stm1 <= $max_STM1} {incr stm1 0x1} {
      for {set stm0 0x0} {$stm0 <= 0x2} {incr stm0 0x1} {        
             
        # Defining CM1 register address offset for link 1 and write 
        # settings
        set addr_CM1 [expr 0x2780 + [expr $stm1 << 2]|[expr $stm0 << 0]]
        admwrb $devID $addr_CM1 6 0 
        admwrb $devID $addr_CM1 5 0 
      }
    }   
  }   
   
  ##############################################################
  #### 4. Configuring the Egress Connection Memory (CM1 and ####
  ####    CM2) to setup egress traffic mapping.	  	    ####
  ##############################################################
  
  # The following lines setup the LOSU CM1 and CM2 with 
  # straight-through mappings.  Each protection group is from the 
  # same ingress source.  All paths are configured to the same 
  # payload types.    
  
  if {$payload == "VT15" || $payload == "AU3/TU11" || $payload == "AU4/TU11"} {  
    
    ### VT 1.5 / TU11 ###
    
    for {set stm1 0x0} {$stm1 <= $max_STM1} {incr stm1 0x1} {
      for {set stm0 0x0} {$stm0 <= 0x2} {incr stm0 0x1} {
        for {set tug2 0x0} {$tug2 <= 0x6} {incr tug2 0x1} {
          for {set tu 0x0} {$tu <= 0x3} {incr tu 0x1} {
             
            # Defining CM1 register address offset
            set addr_CM1 [expr 0x2800 + [expr $stm1 << 7]|[expr $stm0 << 5]|[expr $tug2 << 2]|$tu]
            set addr_CM2 [expr 0x3000 + [expr $stm1 << 7]|[expr $stm0 << 5]|[expr $tug2 << 2]|$tu]
          
            # Connection Settings for Connection Memory Page 1
            # straight through mapping            
            set ilink 0
            set istm1 $stm1	
            set istm0 $stm0
            set itug2 $tug2
            set itu $tu            
            set ing_g2i_pos_sel 0x0
    	    set plsize 0x0 ;# 000b
    	    set insais 0
    	    set insuneq 0
                        
            set data [expr ($ing_g2i_pos_sel << 17)|($ilink << 11)|($istm1 << 7)|($istm0 << 5)|($itug2 << 2)|($plsize <<19)|$itu|($insais << 22)|($insuneq << 23)]
            set data [dec2hex $data]
                          
            # Writing Setting to Connection Memory 1
            admwr $devID $addr_CM1 $data
                        
            # Connection Settings for Connection Memory Page 2
            # straight through mapping            
            set ilink 1
            set istm1 $stm1	
            set istm0 $stm0
            set itug2 $tug2
            set itu $tu            
            set ing_g2i_pos_sel 0x0
    	    set plsize 0x0 ;# 000b
                        
            set data [expr ($ing_g2i_pos_sel << 17)|($ilink << 11)|($istm1 << 7)|($istm0 << 5)|($itug2 << 2)|($plsize <<19)|$itu]
            set data [dec2hex $data]
            
            # Writing Setting to Connection Memory 2
            admwr $devID $addr_CM2 $data                        
            
          }
        }         
      }  
    }       
    
  } elseif {$payload == "VT2" || $payload == "AU3/TU12" || $payload == "AU4/TU12"} { 
  
    ### VT2 / TU12 ###
    
    for {set stm1 0x0} {$stm1 <= $max_STM1} {incr stm1 0x1} {
      for {set stm0 0x0} {$stm0 <= 0x2} {incr stm0 0x1} {
        for {set tug2 0x0} {$tug2 <= 0x6} {incr tug2 0x1} {
          for {set tu 0x0} {$tu <= 0x3} {incr tu 0x1} {
             
            # Defining CM1 register address offset
            set addr_CM1 [expr 0x2800 + [expr $stm1 << 7]	   \
            		  |[expr $stm0 << 5]|[expr $tug2 << 2]|$tu]
            set addr_CM2 [expr 0x3000 + [expr $stm1 << 7]	   \
            		  |[expr $stm0 << 5]|[expr $tug2 << 2]|$tu]               

            # Connection Settings for Connection Memory Page 1          
            # Straight through mapping
            set ilink 0
            set istm1 $stm1	
            set istm0 $stm0
            set itug2 $tug2
            set itu $tu            
            set ing_g2i_pos_sel 0x0
    	    set plsize 0x1 ;#001
    	    set insais 0
    	    set insuneq 0

                       
            set data [expr [expr $ing_g2i_pos_sel << 17]|[expr $ilink << 11]|[expr $istm1 << 7]\
            	      |[expr $istm0 << 5]|[expr $itug2 << 2]|$itu |[expr $plsize <<19]|[expr $insais << 22]|[expr $insuneq << 23]]
                          
            # Writing Setting to Connection Memory 1
            admwr $devID $addr_CM1 $data
          
            # Connection Settings for Connection Memory Page 2
            # Straight through mapping
            set ilink 1
            set istm1 $stm1	
            set istm0 $stm0
            set itug2 $tug2
            set itu $tu            
            set ing_g2i_pos_sel 0x0
    	    set plsize 0x1 ;#001
                       
            set data [expr [expr $ing_g2i_pos_sel << 17]|[expr $ilink << 11]|[expr $istm1 << 7]\
            	      |[expr $istm0 << 5]|[expr $itug2 << 2]|$itu |[expr $plsize <<19]]

            # Writing Setting to Connection Memory 2
            admwr $devID $addr_CM2 $data
          }
        }         
      }  
    }      
  
  } elseif {$payload == "VT3"} {
    
    ### VT3 ###
    # Setting payload type for VT2/TU12
    
    for {set stm1 0x0} {$stm1 <= $max_STM1} {incr stm1 0x1} {
      for {set stm0 0x0} {$stm0 <= 0x2} {incr stm0 0x1} {
        for {set tug2 0x0} {$tug2 <= 0x6} {incr tug2 0x1} {
          for {set tu 0x0} {$tu <= 0x3} {incr tu 0x1} {
             
            # Defining CM1 register address offset
            set addr_CM1 [expr 0x2800 + [expr $stm1 << 7]|[expr $stm0 << 5]|[expr $tug2 << 2]|$tu]
            set addr_CM2 [expr 0x3000 + [expr $stm1 << 7]|[expr $stm0 << 5]|[expr $tug2 << 2]|$tu]               
    
            # Connection Settings for Connection Memory Page 1
            # Defining source of traffic - straight through mapping
            set ilink 0
            set istm1 $stm1	
            set istm0 $stm0
            set itug2 $tug2
            set itu $tu            
            set ing_g2i_pos_sel 0x0
            set insais 0
            set insuneq 0
    
	    if {$tu == 0x0 || $tu == 0x1} {
	      set plsize 0x2 ;# 010	
	    } 
	    if {$tu == 0x2 || $tu == 0x3} {
	      set plsize 0x5 ;# 101
	    }
                       
            set data [expr [expr $ing_g2i_pos_sel << 17]|[expr $ilink << 11]|[expr $istm1 << 7]\
            	      |[expr $istm0 << 5]|[expr $itug2 << 2]|$itu|[expr $plsize <<19]|[expr $insais << 22]|[expr $insuneq << 23]]
                          
            # Writing Setting to Connection Memory 1
            admwr $devID $addr_CM1 $data

            # Connection Settings for Connection Memory Page 2
            # Defining source of traffic - straight through mapping
            set ilink 1
            set istm1 $stm1	
            set istm0 $stm0
            set itug2 $tug2
            set itu $tu            
            set ing_g2i_pos_sel 0x0
    
	    if {$tu == 0x0 || $tu == 0x1} {
	      set plsize 0x2 ;# 010	
	    } 
	    if {$tu == 0x2 || $tu == 0x3} {
	      set plsize 0x5 ;# 101
	    }
                       
            set data [expr [expr $ing_g2i_pos_sel << 17]|[expr $ilink << 11]|[expr $istm1 << 7]\
            	      |[expr $istm0 << 5]|[expr $itug2 << 2]|$itu|[expr $plsize <<19]]
          
            # Writing Setting to Connection Memory 2
            admwr $devID $addr_CM2 $data
          }
        }         
      }  
    }      
    
  
  } elseif {$payload == "VT6" || $payload == "AU4/TU2" || $payload == "AU3/TU2"} {
  
    ### VT6/TU2 ###
    # Setting payload type for VT6/TU2
        
    for {set stm1 0x0} {$stm1 <= $max_STM1} {incr stm1 0x1} {
      for {set stm0 0x0} {$stm0 <= 0x2} {incr stm0 0x1} {
        for {set tug2 0x0} {$tug2 <= 0x6} {incr tug2 0x1} {
          for {set tu 0x0} {$tu <= 0x3} {incr tu 0x1} {
             
            # Defining CM1 register address offset
            set addr_CM1 [expr 0x2800 + [expr $stm1 << 7]|[expr $stm0 << 5]|[expr $tug2 << 2]|$tu]
            set addr_CM2 [expr 0x3000 + [expr $stm1 << 7]|[expr $stm0 << 5]|[expr $tug2 << 2]|$tu]               
             
            # Connection Settings for Connection Memory Page 1
            # Straight through mapping
            set ilink 0
            set istm1 $stm1	
            set istm0 $stm0
            set itug2 $tug2
            set itu $tu            
            set ing_g2i_pos_sel 0x0
            set insais 0
            set insuneq 0
    
	    if {$tu == 0x0 } {
	      set plsize 0x3 ;#011	
	    } 
	    if {$tu == 0x1 || $tu == 0x2 || $tu == 0x3} {
	      set plsize 0x5 ;#101
	    }
                       
            set data [expr [expr $ing_g2i_pos_sel << 17]|[expr $ilink << 11]|[expr $istm1 << 7]\
            	      |[expr $istm0 << 5]|[expr $itug2 << 2]|$itu|[expr $plsize <<19]|[expr $insais << 22]|[expr $insuneq << 23]]
                          
            # Writing Setting to Connection Memory 1
            admwr $devID $addr_CM1 $data
            
            # Connection Settings for Connection Memory Page 2
            # Straight through mapping
            set ilink 1
            set istm1 $stm1	
            set istm0 $stm0
            set itug2 $tug2
            set itu $tu            
            set ing_g2i_pos_sel 0x0
    
	    if {$tu == 0x0 } {
	      set plsize 0x3 ;#011	
	    } 
	    if {$tu == 0x1 || $tu == 0x2 || $tu == 0x3} {
	      set plsize 0x5 ;#101
	    }
                       
            set data [expr [expr $ing_g2i_pos_sel << 17]|[expr $ilink << 11]|[expr $istm1 << 7]\
            	      |[expr $istm0 << 5]|[expr $itug2 << 2]|$itu|[expr $plsize <<19]]
                                                            
            # Writing Setting to Connection Memory 2
            admwr $devID $addr_CM2 $data
          }
        }         
      }  
    }   
    
    
  } elseif {$payload == "STS-1" || $payload == "STS-3c" || $payload == "STS-12c" || $payload == "AU3/TU3" || $payload == "AU4-4c" || $payload == "AU4/C4" || $payload == "AU3/C3"} {
   
    ### STS1/STS-Nc ###
    # Setting payload type for STS1
            
    for {set stm1 0x0} {$stm1 <= $max_STM1} {incr stm1 0x1} {
      for {set stm0 0x0} {$stm0 <= 0x2} {incr stm0 0x1} {
        for {set tug2 0x0} {$tug2 <= 0x6} {incr tug2 0x1} {
          for {set tu 0x0} {$tu <= 0x3} {incr tu 0x1} {
             
            # Defining CM1 register address offset
            set addr_CM1 [expr 0x2800 + [expr $stm1 << 7]|[expr $stm0 << 5]|[expr $tug2 << 2]|$tu]
            set addr_CM2 [expr 0x3000 + [expr $stm1 << 7]|[expr $stm0 << 5]|[expr $tug2 << 2]|$tu]               
          
            # Connection Settings for Connection Memory Page 1
            # Straight through mapping
            set ilink 0
            set istm1 $stm1	
            set istm0 $stm0
            set itug2 $tug2
            set itu $tu            
            set ing_g2i_pos_sel 0x0
            set insais 0