pm5337_eos_demo.tcl

用于EOS芯片的驱动程序, 供参考 参考

      ### ii. Poll MEM_BUSY Bit in 0xE508 ###
      Poll_BUSY_Bit $devID 0xE508 15
 
      ### iii. Calculate and Set MEM_ADDR  ###    
      # MEM_ADDR = sts3_ind*84 + sts1_index*28 + vtg_ind*4 + vt_ind + 64
      # where sts3_ind ranges from 0 to 3, sts1_ind ranges from 0 to 2,
      # vtg_ind ranges from 0 to 6, and vt_ind ranges from 0 to 3
      set mem_addr [expr ($sts3_ind*84)+($sts1_ind*28)+($vtg_ind*4)+($vt_ind+64)]         
      admwr $devID 0xE509 $mem_addr
  
      ### iv. Setting Link Configuration Table Memory Value ###   
      # VC_SQ[5:0] = 0x00
      # Group Tag[4:0] = Ethernet Channel = 0x0 to 0x7
      # Inhibit = 0x0
      # Prov/Mode[1:0] = VCG non-LCAS mode = 0x2 
      set group_tag 0x0
      set inhibit 0x0
      set prov_mode 0x2
      set mem_data0 [expr [expr $vc_sq << 10]|[expr $group_tag << 4]|\
                       [expr $inhibit << 3]|$prov_mode]
                     
      admwr $devID 0xE50A $mem_data0	;# bit 15 to 0
      admwr $devID 0xE50B 0x0000	;# bit 31 to 16
      admwr $devID 0xE50C 0x0000	;# bit 47 to 32
      admwr $devID 0xE50D 0x0000	;# bit 63 to 48
  
      ### v. Trigger Indirect Write Access ###
      # MEM_BUSY = 1
      # MEM_RWB = 0
      # MEM_SEL = 0x0
      admwr $devID 0xE508 0x8000  
      
      ### vi. Incrementing SQ by 1 ###
      set vc_sq [expr $vc_sq + 1]
    } 
  }    
         
 set sts3_ind 1
 set sts1_ind 0           
 set vc_sq 28
             
 for {set vtg_ind 0} {$vtg_ind <= 6} {incr vtg_ind} {
   for {set vt_ind 0} {$vt_ind <= 3} {incr vt_ind} {
     ### ii. Poll MEM_BUSY Bit in 0xE508 ###
     Poll_BUSY_Bit $devID 0xE508 15

     ### iii. Calculate and Set MEM_ADDR  ###    
     # MEM_ADDR = sts3_ind*84 + sts1_index*28 + vtg_ind*4 + vt_ind + 64
     # where sts3_ind ranges from 0 to 3, sts1_ind ranges from 0 to 2,
     # vtg_ind ranges from 0 to 6, and vt_ind ranges from 0 to 3
     set mem_addr [expr ($sts3_ind*84)+($sts1_ind*28)+($vtg_ind*4)+($vt_ind+64)]         
     admwr $devID 0xE509 $mem_addr
 
     ### iv. Setting Link Configuration Table Memory Value ###   
     # VC_SQ[5:0] = 0x00
     # Group Tag[4:0] = Ethernet Channel = 0x0 to 0x7
     # Inhibit = 0x0
     # Prov/Mode[1:0] = VCG non-LCAS mode = 0x2 
     set group_tag 0x0
     set inhibit 0x0
     set prov_mode 0x2
     set mem_data0 [expr [expr $vc_sq << 10]|[expr $group_tag << 4]|\
                      [expr $inhibit << 3]|$prov_mode]
                    
     admwr $devID 0xE50A $mem_data0	;# bit 15 to 0
     admwr $devID 0xE50B 0x0000	;# bit 31 to 16
     admwr $devID 0xE50C 0x0000	;# bit 47 to 32
     admwr $devID 0xE50D 0x0000	;# bit 63 to 48
 
     ### v. Trigger Indirect Write Access ###
     # MEM_BUSY = 1
     # MEM_RWB = 0
     # MEM_SEL = 0x0
     admwr $devID 0xE508 0x8000  
     
     ### vi. Incrementing SQ by 1 ###
     set vc_sq [expr $vc_sq + 1]
    } 
  }          
   
  set sts3_ind 2
  set sts1_ind 0           
  set vc_sq 56
  set vc_sq [dec2hex $vc_sq]
              
  for {set vtg_ind 0} {$vtg_ind <= 1} {incr vtg_ind} {
    for {set vt_ind 0} {$vt_ind <= 3} {incr vt_ind} {
      ### ii. Poll MEM_BUSY Bit in 0xE508 ###
      Poll_BUSY_Bit $devID 0xE508 15
  
      ### iii. Calculate and Set MEM_ADDR  ###    
      # MEM_ADDR = sts3_ind*84 + sts1_index*28 + vtg_ind*4 + vt_ind + 64
      # where sts3_ind ranges from 0 to 3, sts1_ind ranges from 0 to 2,
      # vtg_ind ranges from 0 to 6, and vt_ind ranges from 0 to 3
      set mem_addr [expr ($sts3_ind*84)+($sts1_ind*28)+($vtg_ind*4)+($vt_ind+64)]         
      admwr $devID 0xE509 $mem_addr
  
      ### iv. Setting Link Configuration Table Memory Value ###   
      # VC_SQ[5:0] = 0x00
      # Group Tag[4:0] = Ethernet Channel = 0x0 to 0x7
      # Inhibit = 0x0
      # Prov/Mode[1:0] = VCG non-LCAS mode = 0x2 
      set group_tag 0x0
      set inhibit 0x0
      set prov_mode 0x2
      set mem_data0 [expr [expr $vc_sq << 10]|[expr $group_tag << 4]|[expr $inhibit << 3]|$prov_mode]
                     
      admwr $devID 0xE50A $mem_data0	;# bit 15 to 0
      admwr $devID 0xE50B 0x0000	;# bit 31 to 16
      admwr $devID 0xE50C 0x0000	;# bit 47 to 32
      admwr $devID 0xE50D 0x0000	;# bit 63 to 48
  
      ### v. Trigger Indirect Write Access ###
      # MEM_BUSY = 1
      # MEM_RWB = 0
      # MEM_SEL = 0x0
      admwr $devID 0xE508 0x8000  
      
      ### vi. Incrementing SQ by 1 ###
      set vc_sq [expr $vc_sq + 1]
      set vc_sq [dec2hex $vc_sq]
    } 
  }    
                
  ### 2. Configurating Receive Link Configuration Table (RVCP) ###            
  
  set sts3_ind 0
  set sts1_ind 0   
  set exp_sq 0
                  
  for {set vtg_ind 0} {$vtg_ind <= 6} {incr vtg_ind} {
    for {set vt_ind 0} {$vt_ind <= 3} {incr vt_ind} {
  
      ### ii. Poll MEM_BUSY Bit in 0xE508 ###
      Poll_BUSY_Bit $devID 0xE410 15
  
      ### iii. Calculate and Set MEM_ADDR  ###    
      # MEM_ADDR = STS3_index*3 + STS1_index, where STS3_index ranges
      # from 0 to 3, and STS1_index ranges from 0 to 2.        
      #set mem_addr [expr ($sts3_ind * 3) + $sts1_ind]         
      set mem_addr [expr ($sts3_ind*84)+($sts1_ind*28)+($vtg_ind*4)+($vt_ind+64)]     
      admwr $devID 0xE411 $mem_addr
  
      ### iv. Setting Link Configuration Table Memory Value ###   
      # mode[1:0] = VCG non-LCAS = 0x2
      # EXP_SQ_EN = 0x1
      # Inhibit = 0x0
      # EXP_SQ_[6:0] = 0x0 
      # Group Tag[4:0] = Ethernet Channel = 0x0 to 0x7      
      set prov_mode 0x2
      set exp_sq_en 0x1   
      set inhibit 0x0          
      set group_tag 0x0     
      set mem_data0 [expr [expr $exp_sq << 8]|$group_tag]
      set mem_data1 [expr [expr $prov_mode << 2]|[expr $exp_sq_en << 1]|$inhibit]
                     
      admwr $devID 0xE412 $mem_data0	;# bit 15 to 0
      admwr $devID 0xE413 $mem_data1	;# bit 31 to 16
      admwr $devID 0xE414 0x0000	;# bit 47 to 32
      admwr $devID 0xE415 0x0000	;# bit 63 to 48
      admwr $devID 0xE416 0x0000	;# bit 79 to 64
      admwr $devID 0xE417 0x0000	;# bit 95 to 80
      admwr $devID 0xE418 0x0000	;# bit 111 to 96
      admwr $devID 0xE419 0x0000	;# bit 127 to 112
    
      ### iv. Trigger Indirect Write Access ###
      # MEM_BUSY =1
      # MEM_RWB = 0
      # MEM_SEL = 0x0
      admwr $devID 0xE410 0x8000 
                          
      ### vi. Incrementing SQ by 1 ###
      set exp_sq [expr $exp_sq + 1]
    }         
  }    
         
  set sts3_ind 1
  set sts1_ind 0   
  set exp_sq 28
                 
  for {set vtg_ind 0} {$vtg_ind <= 6} {incr vtg_ind} {
    for {set vt_ind 0} {$vt_ind <= 3} {incr vt_ind} {
 
     ### ii. Poll MEM_BUSY Bit in 0xE508 ###
     Poll_BUSY_Bit $devID 0xE410 15
 
     ### iii. Calculate and Set MEM_ADDR  ###    
     # MEM_ADDR = STS3_index*3 + STS1_index, where STS3_index ranges
     # from 0 to 3, and STS1_index ranges from 0 to 2.        
     #set mem_addr [expr ($sts3_ind * 3) + $sts1_ind]         
     set mem_addr [expr ($sts3_ind*84)+($sts1_ind*28)+($vtg_ind*4)+($vt_ind+64)]     
     admwr $devID 0xE411 $mem_addr
 
     ### iv. Setting Link Configuration Table Memory Value ###   
     # mode[1:0] = VCG non-LCAS = 0x2
     # EXP_SQ_EN = 0x1
     # Inhibit = 0x0
     # EXP_SQ_[6:0] = 0x0 
     # Group Tag[4:0] = Ethernet Channel = 0x0 to 0x7      
     set prov_mode 0x2
     set exp_sq_en 0x1   
     set inhibit 0x0          
     set group_tag 0x0      
     set mem_data0 [expr [expr $exp_sq << 8]|$group_tag]
     set mem_data1 [expr [expr $prov_mode << 2]|[expr $exp_sq_en << 1]|$inhibit]
                    
     admwr $devID 0xE412 $mem_data0	;# bit 15 to 0
     admwr $devID 0xE413 $mem_data1	;# bit 31 to 16
     admwr $devID 0xE414 0x0000	;# bit 47 to 32
     admwr $devID 0xE415 0x0000	;# bit 63 to 48
     admwr $devID 0xE416 0x0000	;# bit 79 to 64
     admwr $devID 0xE417 0x0000	;# bit 95 to 80
     admwr $devID 0xE418 0x0000	;# bit 111 to 96
     admwr $devID 0xE419 0x0000	;# bit 127 to 112
   
     ### iv. Trigger Indirect Write Access ###
     # MEM_BUSY =1
     # MEM_RWB = 0
     # MEM_SEL = 0x0
     admwr $devID 0xE410 0x8000 
                         
     ### vi. Incrementing SQ by 1 ###
     set exp_sq [expr $exp_sq + 1]
   }         
  }
   
  set sts3_ind 2
  set sts1_ind 0   
  set exp_sq 56
  set exp_sq [dec2hex $exp_sq]
                  
  for {set vtg_ind 0} {$vtg_ind <= 1} {incr vtg_ind} {
    for {set vt_ind 0} {$vt_ind <= 3} {incr vt_ind} {
  
      ### ii. Poll MEM_BUSY Bit in 0xE508 ###
      Poll_BUSY_Bit $devID 0xE410 15
  
      ### iii. Calculate and Set MEM_ADDR  ###    
      # MEM_ADDR = STS3_index*3 + STS1_index, where STS3_index ranges
      # from 0 to 3, and STS1_index ranges from 0 to 2.        
      #set mem_addr [expr ($sts3_ind * 3) + $sts1_ind]         
      set mem_addr [expr ($sts3_ind*84)+($sts1_ind*28)+($vtg_ind*4)+($vt_ind+64)]     
      admwr $devID 0xE411 $mem_addr
  
      ### iv. Setting Link Configuration Table Memory Value ###   
      # mode[1:0] = VCG non-LCAS = 0x2
      # EXP_SQ_EN = 0x1
      # Inhibit = 0x0
      # EXP_SQ_[6:0] = 0x0 
      # Group Tag[4:0] = Ethernet Channel = 0x0 to 0x7      
      set prov_mode 0x2
      set exp_sq_en 0x1   
      set inhibit 0x0          
      set group_tag 0x0     
      set mem_data0 [expr [expr $exp_sq << 8]|$group_tag]
      set mem_data1 [expr [expr $prov_mode << 2]|[expr $exp_sq_en << 1]|$inhibit]
                     
      admwr $devID 0xE412 $mem_data0	;# bit 15 to 0
      admwr $devID 0xE413 $mem_data1	;# bit 31 to 16
      admwr $devID 0xE414 0x0000	;# bit 47 to 32
      admwr $devID 0xE415 0x0000	;# bit 63 to 48
      admwr $devID 0xE416 0x0000	;# bit 79 to 64
      admwr $devID 0xE417 0x0000	;# bit 95 to 80
      admwr $devID 0xE418 0x0000	;# bit 111 to 96
      admwr $devID 0xE419 0x0000	;# bit 127 to 112
    
      ### iv. Trigger Indirect Write Access ###
      # MEM_BUSY =1
      # MEM_RWB = 0
      # MEM_SEL = 0x0
      admwr $devID 0xE410 0x8000 
                          
      ### vi. Incrementing SQ by 1 ###
      set exp_sq [expr $exp_sq + 1]
      set exp_sq [dec2hex $exp_sq]
    }         
  }                                                
        
  ### Enable RVCP and TVCP ###  
  # Enabling RVCP block  

  # Mode 0, 1 and 3 carry SONET traffic; therefore,
  # set SDH_SEL = 0 and RVCP_ENABLE  = 1 
  admwr $devID 0xE400 0x8000    
  
  # Mode 0, 1 and 3 carry SONET traffic; therefore,
  # set SONET_SDH_SEL = 0, TVCP_ENABLE = 1, PTR == 522, SS = 10
  admwr $devID 0xE500 0x920A
}


#------------------------------------------------------------------------------
# PROC NAME:  EOS_Counter_Demo
#
# DESCRIPTION:  This procedure is a wrapper to a system specific 
#		'read' function.  
#
# PARAMETERS:	devID  - This parameter is used to specify the device 
#                        under configuration.  If devID is -1, this function
#                        is echo on the TCL console.
# 
#               iChannel - 0 to 7
# 		
# NOTES: 
#
#------------------------------------------------------------------------------

proc EOS_Counter_Demo {devID iChannel {clrMacCnt 1}} {

# iChannel is 0-based.
    
  ### 1 Ensure AUTO PMON transfer and external PMON_I pin are disable ###
  admwr 0 0x0802 0x11F40
  
  # Initialize counter transfer
  admwr 0 0xE004 0x0001  
  after 5
       
  
  ### 2. MSTAT Counter Status ###
  puts "MSTAT Counter Status"
  puts ""
  
  admwr 0 0xEE04 0x8000
  if {$clrMacCnt == 1} {
    admwr 0 0xEE03 [format "0x%x" [expr ($iChannel << 4) | 0x2]]
  } else {
    admwr 0 0xEE03 [format "0x%x" [expr ($iChannel << 4) | 0x1]]
  }
  after 1
  set frrxokl_15_0 [admrd 0 0xEE10]
  set frrxokm_15_0 [admrd 0 0xEE11]
  puts "FRRXOK_LSB(15:0) = $frrxokl_15_0"
  puts "FRRXOK_MSB(15:0) = $frrxokm_15_0"
  puts ""
  
  set frtxokl_15_0 [admrd 0 0xEE34]
  set frtxokm_15_0 [admrd 0 0xEE35]
  puts "FRTXOK_LSB(15:0) = $frtxokl_15_0"
  puts "FRTXOK_MSB(15:0) = $frtxokm_15_0"
  puts ""
    
  set fcserrl_15_0 [admrd 0 0xEE24]
  set fcserrm_15_0 [admrd 0 0xEE25]
  puts "FCSERR_LSB(15:0) = $fcserrl_15_0"
  puts "FCSERR_MSB(15:0) = $fcserrm_15_0"
  
  set l1errl_15_0 [admrd 0 0xEE28]
  set l1errm_15_0 [admrd 0 0xEE29]
  set l1errh_7_0 [admrd 0 0xEE2a]
  puts "L1ERR_LSB(15:0) = $l1errl_15_0"
  puts "L1ERR_MSB(15:0) = $l1errm_15_0"
  puts "L1ERR_HSB(7:0) = $l1errh_7_0"
  puts ""
    
  set l2errl_15_0 [admrd 0 0xEE2c]
  set l2errm_15_0 [admrd 0 0xEE2d]
  set l2errh_7_0 [admrd 0 0xEE2e]
  puts "L2ERR_LSB(15:0) = $l2errl_15_0"
  puts "L2ERR_MSB(15:0) = $l2errm_15_0"
  puts "L2ERR_HSB(7:0) = $l2errh_7_0"
  puts ""
        
  ### 3. RXDP Counter Status ###
  puts "RXDP Counter Status"
  puts ""
  
  # Reading RX_FRM_CNT[31:0] for port/channel 1
  set ireg_grp 0x8
  #set chan 0x0
  set chan $iChannel
  set iaddr [expr 0xC000 | ($ireg_grp << 5) | $chan]
  
  admwr 0 0xE601 $iaddr
  set rx_frm_cnt_15_0 [admrd 0 0xE602]
  set rx_frm_cnt_31_16 [admrd 0 0xE603]
  puts "RX_FRM_CNT (15:0) = $rx_frm_cnt_15_0"
  puts "RX_FRM_CNT (31:16) = $rx_frm_cnt_31_16"
  puts ""
  
  # Reading DROP_FRM_CNT[31:0] for port/channel 1
  set ireg_grp 0xA
  #set chan 0x0
  set chan $iChannel
  set iaddr [expr 0xC000 | ($ireg_grp << 5) | $chan]
  
  admwr 0 0xE601 $iaddr
  set drop_frm_cnt_15_0 [admrd 0 0xE604]
  set drop_frm_cnt_31_16 [admrd 0 0xE605]
  
  puts "DROP_FRM_CNT (15:0) = $drop_frm_cnt_15_0"
  puts "DROP_FRM_CNT (31:16) = $drop_frm_cnt_31_16"
  puts ""
  
  
  ### 4. TXDP Counter Status ###
  puts "TXDP Status"
  puts ""
  # Reading TX_FRM_CNT
  #admwr 0 0xE719 0x8000    
  admwr 0 0xE719 [format "0x%x" [expr 0x8000 | $iChannel]]
  
  set tx_frm_cnt_15_0 [admrd 0 0xE71D]
  set tx_frm_cnt_31_16 [admrd 0 0xE71E]
  puts "TX_FRM_CNT ( 15:0) = $tx_frm_cnt_15_0"
  puts "TX_FRM_CNT (31:16) = $tx_frm_cnt_31_16"
  puts ""
  
  # Displaying IBUF Counter Status
  puts "IBUF Status"
  puts ""
  #set fifo_ovr_pkt_cnt_15_0 [admrd 0 0xEB42]
  set iAddr [format "0x%x" [expr 0xEB42 + 2*$iChannel]]  
  set fifo_ovr_pkt_cnt_15_0 [admrd 0 $iAddr]
  set iAddr [format "0x%x" [expr 0xEB43 + 2*$iChannel]]
  set fifo_ovr_pkt_cnt_31_16 [admrd 0 $iAddr]
  
  puts "FIFO_OVR_PKT_CNT (15:0) = $fifo_ovr_pkt_cnt_15_0"
  puts "FIFO_OVR_PKT_CNT (31:16) = $fifo_ovr_pkt_cnt_31_16"
  
}

proc eos_gfpState {iChannel} {
  set iAddr [format "0x%x" [expr 0xE711 + $iChannel]]
  puts "TXDP Reg $iAddr : [admrd 0 $iAddr]"
  
  set iAddr [format "0x%x" [expr 0xE620 + $iChannel]]
  puts "RXDP Reg $iAddr : [admrd 0 $iAddr]"
  
}