pm5337_sys_sonet.tcl

用于EOS芯片的驱动程序, 供参考 参考

      admwr $devID $addr_0x0701 0x7101
      admwr $devID $addr_0x0702 0x0041 
      admwr $devID $addr_0x0703 0x00CC
    } 
    if {$scr_descr_mode == 1} {  
      admwr $devID $addr_0x0622 0x0101 
      admwr $devID $addr_0x0623 0x0041 
      admwr $devID $addr_0x0624 0x008C 
      
      admwr $devID $addr_0x0701 0x07101
      admwr $devID $addr_0x0702 0x0041 
      admwr $devID $addr_0x0703 0x008C      
    } 
    if {$scr_descr_mode == 2} {  
      admwr $devID $addr_0x0622 0x0084 
      admwr $devID $addr_0x0623 0x004A 
      admwr $devID $addr_0x0624 0x0083 
      
      admwr $devID $addr_0x0701 0x7084
      admwr $devID $addr_0x0702 0x004A 
      admwr $devID $addr_0x0703 0x0083      
    }  
    if {$scr_descr_mode == 3} {  
      admwr $devID $addr_0x0622 0x00C1 
      admwr $devID $addr_0x0623 0x0041 
      admwr $devID $addr_0x0624 0x008C 
      
      admwr $devID $addr_0x0701 0x70C1
      admwr $devID $addr_0x0702 0x0041 
      admwr $devID $addr_0x0703 0x008C      
    } 
  }
  
  #############################
  ##### Centering Tx FIFO #####
  #############################
  # It is recommended to perform a FIFO centering operation after each 
  # device reset.  (Register 0x0700 + 0x10(n-1))

  admwrb $devID $addr_0x0700 11 1
  admwrb $devID $addr_0x0700 10 1
   
  # Configure Frame Pulse Delay Registers  [Updated in Released 2]
  
  # Add/drop mode
  if {$mode == 0} { 
    if {$rate == 0} {      
      # Assume all 622.08 Mbps links, if mixing 622M/2.5G links
      # set dly to 0x97CD
      admwr $devID [dec2hex [expr 0x0806 + $link]] 0x25EE
    }
    if {$rate == 1} {
      # Assume all 2.5 Gbps links, if mixing 622M/2.5G links
      # set dly to 0x97D6
      admwr $devID [dec2hex [expr 0x0806 + $link]] 0x97D6
    }
  }
  
  # Companion mode
  if {$mode == 1} { 
    if {$rate == 0} {      
      # Assume all 622.08 Mbps links, if mixing 622M/2.5G links
      # set dly to 0x009D
      admwr $devID [dec2hex [expr 0x0806 + $link]] 0x0036
      
      # Assume all 2.5 Gbps links, if mixing 622M/2.5G links
      # set dly to 0x002A
      admwr $devID 0x080F 0x003E
    }
    if {$rate == 1} {      
      # Assume all 2.5 Gbps links, if mixing 622M/2.5G links
      # set dly to 0x00A6
      admwr $devID [dec2hex [expr 0x0806 + $link]] 0x0096
      
      # Assume all 2.5 Gbps links, if mixing 622M/2.5G links
      # set dly to 0x002A
      admwr $devID 0x080F 0x0026
    }       
            
  }
    
}

#-------------------------------------------------------------------
# SCRIPT NAME:	SYS_SONET_SMART_Framing
#
# DESCRIPTION:	This procedure calculates the AFPDLY value for the
#               system side Add ESSI links.
#               
# PARAMETERS:	devID 
#
# NOTE:		This procedues assumes all ESSI links are configured
#               to 2.488 Gbps mode.  This procedure needs to be modified
#               for 622.08 Mbps mode.
#
#-------------------------------------------------------------------

proc SYS_SONET_SMART_Framing {devID} {

  source /usr/lib/cgi-bin/apps/tclscripts/PM5337_util.tcl  

  if {$devID != -1} {      
    ##### 1. Check OOF status on all RX links #####
    
    # Check all SYS_SONET PTCB RSDM to determine which 	 
    # links are in frame (ie. OOFV = 0).  If a link is in OOF,  
    # the Diff_J0[15:0] value will not be used for calculation. 
    
    # Check RSDM OOFV bit status in PTCB and ESSI 1 to 4
    # RSDM1 = PTCB
    # RSDM2 = ESSI Link 1
    # RSDM3 = ESSI Link 2
    # RSDM4 = ESSI Link 3
    # RSDM5 = ESSI Link 4
    
    set OOF_RSDM1 [admrdb $devID 0x0427 1]
    set OOF_RSDM2 [admrdb $devID 0x0627 1]
    set OOF_RSDM3 [admrdb $devID 0x0647 1]
    set OOF_RSDM4 [admrdb $devID 0x0667 1]
    set OOF_RSDM5 [admrdb $devID 0x0687 1]
   
    ## Check if at least one link is in frame ##
    if {$OOF_RSDM1 == 1 && $OOF_RSDM2 == 1 && $OOF_RSDM3 == 1 && $OOF_RSDM4 == 1 && $OOF_RSDM5 == 1} {      
      puts "SMART Framing Abort:  All RSDM Rx links are Out-Of-Frame."    
      return   
    }
       
    ##### 2. Trigger a transfer of Diff_J0 to holding register #####
    
    # Make sure AFPDLY (lower 16 bits of 0x0805) are 0x0000
    # Set upper 12 bits of 0x0805 to 0x208
    admwr $devID 0x0805 [expr [admrd $devID 0x0805] & 0x000F0000 |[expr 0x280 << 20]]
    
    ### Initialize DIFF_J0 value transfer ###
    # Line 1 (PTCB)
    admwr $devID 0x0428 0x0000  
    # Line 2 (ESSI1)
    admwr $devID 0x0628 0x0000  
    # Line 3 (ESSI2)
    admwr $devID 0x0648 0x0000  
    # Line 4 (ESSI3)
    admwr $devID 0x0668 0x0000  
    # Line 5 (ESSI4)
    admwr $devID 0x0688 0x0000  
       
    ##### 3. Wait for TIP_DIFF_J0 to clear #####
    # Poll TIP_DIFF_J0 bit until low             
    Poll_BUSY_Bit $devID 0x0427 2 ;# PTCB
    Poll_BUSY_Bit $devID 0x0627 2 ;# ESSI Link #1
    Poll_BUSY_Bit $devID 0x0647 2 ;# ESSI Link #2
    Poll_BUSY_Bit $devID 0x0667 2 ;# ESSI Link #3
    Poll_BUSY_Bit $devID 0x0687 2 ;# ESSI Link #4
    
         
    ##### 4. Calculate Frame Pulse Delay Value #####
    # Line 1
    if {$OOF_RSDM1 == 0} {
      set j0_diff_1 [admrd $devID 0x0428]
    } elseif {$OOF_RSDM1 == 1} {
      set j0_diff_1 -1
    }
   # Line 2
    if {$OOF_RSDM2 == 0} {
      set j0_diff_2 [admrd $devID 0x0628]
    } elseif {$OOF_RSDM2 == 1} {
      set j0_diff_2 -1
    }
    # Line 3
    if {$OOF_RSDM3 == 0} {
      set j0_diff_3 [admrd $devID 0x0648]
    } elseif {$OOF_RSDM4 == 1} {
      set j0_diff_4 -1
    }
    # Line 4
    if {$OOF_RSDM4 == 0} {
      set j0_diff_4 [admrd $devID 0x0668]
    } elseif {$OOF_RSDM4 == 1} {
      set j0_diff_4 -1
    }
    # Line 5
    if {$OOF_RSDM5 == 0} {
      set j0_diff_5 [admrd $devID 0x0688]
    } elseif {$OOF_RSDM5 == 1} {
      set j0_diff_5 -1
    }
      
    #### (b) Find maximum DIFF_J0 for wrap around checking ####
    set j0_max_tmp 0
    
    if {$j0_diff_1 > $j0_max_tmp} {
        set j0_max_tmp $j0_diff_1
    } 
    if {$j0_diff_2 > $j0_max_tmp} {
        set j0_max_tmp $j0_diff_2
    } 
    if {$j0_diff_3 > $j0_max_tmp} {
        set j0_max_tmp $j0_diff_3
    } 
    if {$j0_diff_4 > $j0_max_tmp} {
        set j0_max_tmp $j0_diff_4
    } 
    if {$j0_diff_5 > $j0_max_tmp} {
        set j0_max_tmp $j0_diff_5
    } 
    
    #### (c) Check for wrap around ####
    
    if {[expr ($j0_max_tmp - $j0_diff_1)] >= 104 && $j0_diff_1 != -1} {
      set $j0_diff_1 [expr $j0_diff_1 + 38880]
    }
    if {[expr ($j0_max_tmp - $j0_diff_2)] >= 104 && $j0_diff_2 != -1} {
      set $j0_diff_2 [expr $j0_diff_2 + 38880]
    }
    if {[expr ($j0_max_tmp - $j0_diff_3)] >= 104 && $j0_diff_3 != -1} {
      set $j0_diff_3 [expr $j0_diff_3 + 38880]
    }
    if {[expr ($j0_max_tmp - $j0_diff_4)] >= 104 && $j0_diff_4 != -1} {
      set $j0_diff_4 [expr $j0_diff_4 + 38880]
    }
    if {[expr ($j0_max_tmp - $j0_diff_5)] >= 104 && $j0_diff_5 != -1} {
      set $j0_diff_5 [expr $j0_diff_5 + 38880]
    }
    
    #### (d) Check for Min and Max ####  
    set j0_max_adj 0
    set j0_min_adj 77760	;# 2x maxcnt
    
    # finding j0_max_adj     
    if {$j0_diff_1 > $j0_max_adj && $j0_diff_1 != -1} {
        set j0_max_adj $j0_diff_1
    } 
    if {$j0_diff_2 > $j0_max_adj && $j0_diff_2 != -1} {
        set j0_max_adj $j0_diff_2
    }
    if {$j0_diff_3 > $j0_max_adj && $j0_diff_3 != -1} {
        set j0_max_adj $j0_diff_3
    } 
    if {$j0_diff_4 > $j0_max_adj && $j0_diff_4 != -1} {
        set j0_max_adj $j0_diff_4
    } 
    if {$j0_diff_5 > $j0_max_adj && $j0_diff_5 != -1} {
        set j0_max_adj $j0_diff_5
    } 
     
    # finding j0_min_adj
    if {$j0_diff_1 < $j0_min_adj && $j0_diff_1 != -1} {
        set j0_min_adj $j0_diff_1
    } 
    if {$j0_diff_2 < $j0_min_adj && $j0_diff_2 != -1} {
        set j0_min_adj $j0_diff_2
    } 
    if {$j0_diff_3 < $j0_min_adj && $j0_diff_3 != -1} {
        set j0_min_adj $j0_diff_3
    } 
    if {$j0_diff_4 < $j0_min_adj && $j0_diff_4 != -1} {
        set j0_min_adj $j0_diff_4
    } 
    if {$j0_diff_5 < $j0_min_adj && $j0_diff_5 != -1} {
        set j0_min_adj $j0_diff_5
    } 
    
    #### (e) Determine the FIFO midpoint ####
    set midpoint [expr ($j0_min_adj + $j0_max_adj)/2]
    
    #### (f) Determining the delay offset ####
    set maxcnt 38880
    set fifosize 104
    set fpdly_offset [expr $maxcnt - 1 - $midpoint + $fifosize/2 - 1]
    
    if {$fpdly_offset > $maxcnt} {
      set fpdly_offset [expr $fpdly_offset - $maxcnt]
    }
      
    # Store FP_DLY in lower 16 bits of 0x805
    admwr $devID 0x0805 [expr [admrd $devID 0x0805] & 0xFFFF0000 | $fpdly_offset]    
    puts "The ADD ESSI Frame Pulse Delay value is $fpdly_offset"
  
  } 
  
  if {$devID == -1} {
    # Display log on TCL console
    puts "Performing SMART Framing on ESSI Links and PTCB, see SYS_SONET_SMART_Framing for more information <br>"
  }
     
}