pm5337_eos.tcl

用于EOS芯片的驱动程序, 供参考 参考

            # 3. Specify tributary address and set RWB = 0	
            set rwb 0
            set iaddr_value [expr ($rwb << 14) | ($stm1 << 8) | ($tug3 << 6) | ($tug2 << 3) | $tu]
            set iaddr_value [dec2hex $iaddr_value]
  	      	    
  	    admwr $devID 0xE381 $iaddr_value

            # 4. Poll BUSY bit until it is low (Optional step)
            # Poll_BUSY_Bit $devID 0xE381 15
          }
        }
      }
    }
  }         
    
  ### TRAP336 Configuration ###
  # If the data stream contain VT/TUs, set TRAP336 Payload Configuration.
  # Note that the STM-4/STS-12 data stream are configured to carry the 
  # same tributary types.
  
  if {$activeTU != 0} {          
    for {set stm1 1} {$stm1 <= 4} {incr stm1} {
      for {set tug3 1} {$tug3 <= 3} {incr tug3} {
        for {set tug2 1} {$tug2 <= 7} {incr tug2} {
          #for {set tu 1} {$tu <= $activeTU} {incr tu} {
            
            set tu 1
                
            # 1. Poll BUSY bit until it is low
            Poll_BUSY_Bit $devID 0xE3C2 15
          
            # 2. Set Tributary Type in VTPI Indirect Configuration Register
            if {$payload == "AU4/TU12" ||$payload == "AU3/TU12"} {
              admwr $devID 0xE3C3 0x0080
            } elseif {$payload == "VT15"} {
              admwr $devID 0xE3C3 0x00C0
            }          	
            # 3. Specify tributary address and set RWB = 0	
            set rwb 0
            set iaddr_value [expr [expr $rwb << 14]|[expr $stm1 << 8]|[expr $tug3 << 6]|\
                            [expr $tug2 << 3]|$tu]          
  	    admwr $devID 0xE3C2 $iaddr_value

            # 4. Poll BUSY bit until it is low (Optional step)
            # Poll_BUSY_Bit $devID 0xE3C2 15
          #}
        }
      }
    }
  }              
  
}

#------------------------------------------------------------------------------
# SCRIPT NAME:	EOS_FE_VCG_Config
#
# DESCRIPTION:	This procedure initialize and configure the Virtual Concatenation
#               Processor (RVCP and TVCP).
#		
# PARAMETERS:   devID - This parameter is used to specify the device 
#                       under configuration
#
#		mode - Valid values are 0 to 4, see notes for descriptions:
#                 
# NOTES:  1) mode is defined as follow:
#
#         mode  | VCG_LCAS/     | Payload |        Mapping to SONET/SDH
#               | VCG_non-LCAS/ |         |
#               | Transparent   |         |
#        =================================================================================
#          0    | Transparent   |  STS-1  |  STS1: 1  2  3  4  5  6  7  8  9  10 11 12
#               |               |         |  Chan: 0  1  2  3  4  5  6  7  X  X  X  X
#        ---------------------------------------------------------------------------------
#          1    | VCG_non-LCAS  | VT1.5   |  STS3: 1  2  3  4  1  2  3  4  1  2  3  4
#               |               |         |  STS1: 1  1  1  1  2  2  2  2  3  3  3  3
#               |               |         |  Chan: 0  1  2  3  4  5  6  7  X  X  X  X
#        Note: Channel 0 is mapped to 28 VT1.5 in STS-1 #1 following the SONET order, 
#              channel 1 is mapped to 28 VT1.5 in STS-1 #2 following the SONET order, 
#              etc.
#        ---------------------------------------------------------------------------------
#          2    | VCG_non-LCAS  | TU12    |  STM1: 1  2  3  4  1  2  3  4  1  2  3  4
#               |               |         |  STM0: 1  1  1  1  2  2  2  2  3  3  3  3
#               |               |         |  Chan: 0  1  2  3  4  5  6  7  X  X  X  X
#        Note: Channel 0 is mapped to 21 VC12 in STM1#1/STM0#1 following the SONET order, 
#              channel 1 is mapped to 21 VC12 in STM1#2/STM0#1 following the SONET order,
#              etc.
#        ---------------------------------------------------------------------------------
#          3    | VCG_LCAS      | VT1.5   |  STS3: 1  2  3  4  1  2  3  4  1  2  3  4
#               |               |         |  STS1: 1  1  1  1  2  2  2  2  3  3  3  3
#               |               |         |  Chan: 0  1  2  3  4  5  6  7  X  X  X  X
#        Note: Channel 0 will occupy the VT1.5s in STS-1 #1, channel 1 will occupy the VT1.5 
#              in STS-1 #2, etc.
#        ---------------------------------------------------------------------------------
#          4    | VCG_LCAS      | TU12    |  STM1: 1  2  3  4  1  2  3  4  1  2  3  4
#               |               |         |  STM0: 1  1  1  1  2  2  2  2  3  3  3  3
#               |               |         |  Chan: 0  1  2  3  4  5  6  7  X  X  X  X
#        Note: Channel 0 will occupy the VC2s in STS-1 #1, channel 1 will occupy the VC2 
#              in STS-1 #2, etc.
#
#       2) For mode 3 and 4, after EOS_FE_VCG_Config is completed, call EOS_LCAS_Config  
#          to add or drop a VCG member.
#
#------------------------------------------------------------------------------------------


proc EOS_FE_VCG_Config {devID mode} {

  source /usr/lib/cgi-bin/apps/tclscripts/PM5337_util.tcl  

  #######################################################################
  ###      Initializing TVCP - Far End Sink (MST) Buffer and Group    ###
  ###                    Context Memory                               ###
  #######################################################################
  
  ##### 1. Initializing MST Buffer #####
  # Note: All MST must be initialized to FAIL when provisioning the
  #       first member for a group or if all the members in the group
  #       are in IDLE.
    
  for {set grouptag 0} {$grouptag <= 7} {incr grouptag} {
    for {set wordoffset 0} {$wordoffset <= 7} {incr wordoffset} {
  
      ### i. Poll MEM_BUSY Bit in 0xE508 ###
      Poll_BUSY_Bit $devID 0xE508 15
  
      ### ii. Calculate and Set MEM_ADDR  ###
      # MEM_ADDR = Group-Tag *8 + Word Offset
      set mem_addr [expr $grouptag*8 + $wordoffset]            
      admwr $devID 0xE509 $mem_addr
      
      ### iii. Setting FE SK MST Value ###
      admwr $devID 0xE50A 0x00FF	;# bit 15 to 0
      admwr $devID 0xE50B 0x0000	;# bit 31 to 16
      admwr $devID 0xE50C 0x0000	;# bit 47 to 32
      admwr $devID 0xE50D 0x0000	;# bit 63 to 48
      
      ### iv. Trigger Indirect Write Access ###
      # MEM_BUSY = 1
      # MEM_RWB = 0
      # MEM_SEL = 0x1
      admwr $devID 0xE508 0x8001      
    }
  }
  
  ##### 2. Initializing Group Context Memory #####
  # Note: GID_SEED allows software to program an initial seed
  #       for the GID generation of each group, which should
  #       be done prior to provisioning the first member for the
  #       group.  A unique and non-zero seed for each group should
  #       be set.  In the following example, the group seed is set
  #       to be equal to the grouptag (i.e. channel #)

  set wordoffset 0x2    
  for {set grouptag 0} {$grouptag <= 7} {incr grouptag} {
 
      ### i. Poll MEM_BUSY Bit in 0xE508 ###
      Poll_BUSY_Bit $devID 0xE508 15
  
      ### ii. Calculate and Set MEM_ADDR  ###
      # MEM_ADDR = Group-Tag *3 + Word Offset
      set mem_addr [expr $grouptag*3 + $wordoffset]            
      admwr $devID 0xE509 $mem_addr
      
      ### iii. Randomly asign GID seed = grouptag ###
      admwr $devID 0xE50A $grouptag	;# bit 15 to 0 	
      admwr $devID 0xE50B 0x0000   	;# bit 31 to 16
      admwr $devID 0xE50C 0x0000   	;# bit 47 to 32
      admwr $devID 0xE50D 0x0000   	;# bit 63 to 48
      
      ### iv. Trigger Indirect Write Access ###
      # MEM_BUSY = 1
      # MEM_RWB = 0
      # MEM_SEL = 0x2
      admwr $devID 0xE508 0x8002      
  }      
  
  #######################################################################
  ##### Initializing RVCP - Near End Source (MST) Buffer and Group  #####
  #####                    Configuration Table Memory Structure     #####
  #######################################################################

  ##### 1. Initializing MST Buffer #####
  # Note: All MST must be initialized to FAIL when provisioning the
  #       first member for a group or if all the members in the group
  #       are in IDLE.
    
  for {set grouptag 0} {$grouptag <= 7} {incr grouptag} {
 
    ### i. Poll MEM_BUSY Bit in 0xE508 ###
    Poll_BUSY_Bit $devID 0xE410 15
  
    ### ii. Calculate and Set MEM_ADDR  ###
    # MEM_ADDR = Group-Tag            
    admwr $devID 0xE411 $grouptag
      
    ### iii. Setting NE SK MST Value ###
    admwr $devID 0xE412 0x00FF	;# bit 15 to 0
    admwr $devID 0xE413 0x0000	;# bit 31 to 16
    admwr $devID 0xE414 0x0000	;# bit 47 to 32
    admwr $devID 0xE415 0x0000	;# bit 63 to 48
    admwr $devID 0xE416 0x0000	;# bit 79 to 64
    admwr $devID 0xE417 0x0000	;# bit 95 to 80
    admwr $devID 0xE418 0x0000	;# bit 111 to 96
    admwr $devID 0xE419 0x0000	;# bit 127 to 112
      
    ### iv. Trigger Indirect Write Access ###
    # MEM_BUSY =1
    # MEM_RWB = 0
    # MEM_SEL = 0xB
    admwr $devID 0xE410 0x800B
       
  }

  ##### 2. Configuring Group Configuration Table Memory Structure #####    
  # The tolerable differential delay for a VCG is expressed in terms of the 
  # number of multiframes (MAX_DELAY_MFI2) plus the number of SONET/SDH frame
  # bytes (MAX_DELAY_OFFSET).  The following procedure determine these values.
  
  ### i) Determine the number of SONET/SDH skewed frames ###
  # In this example, the maximum skew 64 ms is used.  To find the skew_frames:
  # skew_frames = differential delay [ms] / 0.125 ms
  # skew_frames = 64 ms/ 0.125 ms = 512
   
  set skew_frames 512
  
  ### ii) Calculate MAX_DELAY_MFI2 and MAX_DELAY_OFFSET ###
  # For high order payload, MAX_DELAY_MFI2 = Truncate (skew_frames/16), and
  # for low order payload, MAX_DELAY_MFI2 = Truncate (skew_frames/128).
  
  # To find MAX_DELAY_OFFSET use the following equation:
  #   For STS-3c/VC-4, MAX_DELAY_OFFSET = ROUNDUP((skew_frames MOD 16) * 146.25) + 6
  #   For STS-1/VC-3, MAX_DELAY_OFFSET = ROUNDUP((skew_frames MOD 16) * 47.25) + 6
  #   For VT1.5, MAX_DELAY_OFFSET = ROUNDUP((skew_frames MOD 128) * 1.5625) + 6
  #   For TU12, MAX_DELAY_OFFSET = ROUNDUP((skew_frames MOD 128) * 2.125) + 6
  #
  #  In this example, using the above equation, max_delay_mfi2 and max_delay_offset
  #  for mode 0 to 4 are:  
  #  Mode     max_delay_mfi2      max_delay_offset
  # ------------------------------------------------
  #  0            0x20 (32d)          0x6
  #  1            0x4                 0x6
  #  2            0x4                 0x6   
  #  3            0x4                 0x6
  #  4            0x4                 0x6
      
  if {$mode == 0} {
      set max_delay_mfi2 0x20
      set max_delay_offset 0x6
  } else {
      set max_delay_mfi2 0x4
      set max_delay_offset 0x6
  }  
  
  ### iii) Write Settings to registers ###  
  for {set grouptag 0} {$grouptag <= 7} {incr grouptag} {
 
    ### i. Poll MEM_BUSY Bit in 0xE508 ###
    Poll_BUSY_Bit $devID 0xE410 15
  
    ### ii. Calculate and Set MEM_ADDR  ###
    # MEM_ADDR = Group-Tag            
    admwr $devID 0xE411 $grouptag
     
    ### iii. Setting FE SK MST Value ###                  
    set mem_data0 [expr 0xFFFF&[expr $max_delay_mfi2 << 12]|$max_delay_offset]
    set mem_data1 [expr [expr $max_delay_mfi2 & 0x3F] >> 4]
    
    # JR debug
    set mem_data0 0xFFFF
    set mem_data1 0x3  
                
    admwr $devID 0xE412 $mem_data0	;# bit 15 to 0
    admwr $devID 0xE413 $mem_data1	;# bit 31 to 16
    admwr $devID 0xE414 0x0000	;# bit 47 to 32
    admwr $devID 0xE415 0x0000	;# bit 63 to 48
    admwr $devID 0xE416 0x0000	;# bit 79 to 64
    admwr $devID 0xE417 0x0000	;# bit 95 to 80
    admwr $devID 0xE418 0x0000	;# bit 111 to 96
    admwr $devID 0xE419 0x0000	;# bit 127 to 112
      
    ### iv. Trigger Indirect Write Access ###
    # MEM_BUSY =1
    # MEM_RWB = 0
    # MEM_SEL = 0x1
    admwr $devID 0xE410 0x8001     
  }
  
  #######################################################################    
  ######         Provisioning VCG members for Mode 0 to 4           #####  
  #######################################################################    
  #######################################################################
  ###     Provisioning VCG Member for Mode 0 (Transparent STS-1)      ###  
  #######################################################################          
  # timeslot : 1  2  3  4  5  6  7  8  9 10 11 12
  # sts3_ind : 0  1  2  3  0  1  2  3  0  1  2  3
  # sts1_ind : 0  0  0  0  1  1  1  1  2  2  2  2 
  # channel  : 0  1  2  3  4  5  6  7  X  X  X  X 
  #
  # X = Unused STS-1 time slots.
  
  if {$mode == 0} {
    ### 1. Configurating Transmit Link Configuration Table (TVCP) ###     
    for {set channel 0} {$channel <= 7} {incr channel} {      
      # i. Defining SONET to Channel mapping
      if {$channel == 0} {
        set sts3_ind 0
        set sts1_ind 0
      } elseif {$channel == 1} {
        set sts3_ind 1
        set sts1_ind 0
      } elseif {$channel == 2} {
        set sts3_ind 2
        set sts1_ind 0
      } elseif {$channel == 3} {
        set sts3_ind 3
        set sts1_ind 0
      } elseif {$channel == 4} {
        set sts3_ind 0
        set sts1_ind 1
      } elseif {$channel == 5} {
        set sts3_ind 1
        set sts1_ind 1
      } elseif {$channel == 6} {
        set sts3_ind 2
        set sts1_ind 1
      } elseif {$channel == 7} {
        set sts3_ind 3
        set sts1_ind 1
      }
    
      ### ii. Poll MEM_BUSY Bit in 0xE508 ###
      Poll_BUSY_Bit $devID 0xE508 15
 
      ### iii. Calculate and Set MEM_ADDR  ###    
      # MEM_ADDR = STS3_index*3 + STS1_index, where STS3_index ranges
      # from 0 to 3, and STS1_index ranges from 0 to 2.        
      set mem_addr [expr ($sts3_ind * 3) + $sts1_ind]         
      admwr $devID 0xE509 $mem_addr
     
      ### iv. Setting Link Configuration Table Memory Value ###   
      # VC_SQ[5:0] = 0x00
      # Group Tag[4:0] = Ethernet Channel = 0x0 to 0x7
      # Inhibit = 0x0
      # Prov/Mode[1:0] = transparent mode = 0x3 
      set vc_sq 0x0
      set group_tag $channel
      set inhibit 0x0
      set prov_mode 0x3
      set mem_data0 [expr [expr $vc_sq << 10]|[expr $group_tag << 4]|\
                       [expr $inhibit << 3]|$prov_mode]
                         
      admwr $devID 0xE50A $mem_data0	;# bit 15 to 0
      admwr $devID 0xE50B 0x0000	;# bit 31 to 16
      admwr $devID 0xE50C 0x0000	;# bit 47 to 32
      admwr $devID 0xE50D 0x0000	;# bit 63 to 48
      
      ### v. Trigger Indirect Write Access ###
      # MEM_BUSY = 1