pm5337_eos.tcl

用于EOS芯片的驱动程序, 供参考 参考

  set addr_0xEC02 [expr 0xEC02 + ($channel*0x20)]	;# 0xC02 +0x20*N  
  set addr_0xEC03 [expr 0xEC03 + ($channel*0x20)]	;# 0xC03 +0x20*N
  set addr_0xEC04 [expr 0xEC04 + ($channel*0x20)]	;# 0xC04 +0x20*N
  set addr_0xEC05 [expr 0xEC05 + ($channel*0x20)]	;# 0xC05 +0x20*N
  set addr_0xEC06 [expr 0xEC06 + ($channel*0x20)]	;# 0xC06 +0x20*N
  set addr_0xEC07 [expr 0xEC07 + ($channel*0x20)]	;# 0xC07 +0x20*N
  
  ### 1. Setting TMAC Configuration Register #1 ###            
  # Ensure TMAC is disabled during configuration  
  set tmac_enbl 0
  
  # Mapping bit to proper position  
  set value1 [expr 0x0100|[expr $crc_ck << 14]|[expr $pad_add_en << 12]| \
             [expr $crc_add_en << 11]|[expr $min_frm_ck << 10]| \
             [expr $trunc_en << 9]|[expr $ibuf_hthr_en << 6]| \
             [expr $xon_en << 5]|$tmac_enbl]
   
  # Write value1 to TMAC Configuration Register #1
  admwr $devID $addr_0xEC00 $value1
  
  ### 2. Setting TMAC Configuration Register #2 ###    
  set value2 [expr 0x4010|$pamb_len]      
  admwr $devID $addr_0xEC01 $value2
  
  ### 3. Setting Maximum Frame Length ###
  admwr $devID $addr_0xEC06 $max_frm_len
  
  ### 4. Setting Min Frame Length ###   
  set value3 [expr 0x4000 |[expr $min_frm_tag << 6]|$min_frm_len]  
  admwr $devID $addr_0xEC07 $value3
  
  ### 5. Setting TMAC Station Address ###
  admwr $devID $addr_0xEC03 $sta1
  admwr $devID $addr_0xEC04 $sta2
  admwr $devID $addr_0xEC05 $sta3          
  
  ### 6. Setting all RESERVED_0 bits to 0 ###
  admwrb $devID $addr_0xEC01 8 0
  admwrb $devID $addr_0xEC01 7 0
  admwrb $devID $addr_0xEC02 7 0
  admwrb $devID $addr_0xEC02 2 0
  
  ### 7. Enable TMAC Block ###
  admwrb $devID $addr_0xEC00 0 1  
  
}

#------------------------------------------------------------------------------
# SCRIPT NAME:	EOS_DSDC_Init
#
# DESCRIPTION:	This procedure configure the DDR RAM Interface.
#		
# PARAMETERS:   devID - This parameter is used to specify the device 
#                       under configuration
#               caslat - CAS Latency: 0 (2 cycles), 1 (2.5 cycles), 
#                                     2 (3 cycles)
# NOTES:
#
# REVISION HISTORY:
# Preliminary 1 - Scripts created
# Released 2 - Updated DSDC Indirect Configuration Register settings
#------------------------------------------------------------------------------

proc EOS_DSDC_Init {devID caslat} {
     
  source /usr/lib/cgi-bin/apps/tclscripts/PM5337_util.tcl  

  ##########################################
  ##### Initializing DDR RAM Interface #####
  ##########################################
  
  ### Setting Indirect Configuration A Register ###  
  # TPDEX = 1 cycle
  # TRCD = 3 cycles
  # TRRD = 2 cycles
  # TWR = 2 cycles
  # BSTLEN = 4 words
  
  if {$caslat == 0} {
    # CAS Latency is 2 cycles
    set value1 0x5A92
  } elseif {$caslat == 1} {
    # CAS Latency is 2.5 cycles
    set value1 0x5A96
  } elseif {$caslat == 2} {
    # CAS Latency is 3 cycles
    set value1 0x5A93
  }
  
  # Write settings to indirect register
  Poll_BUSY_Bit $devID 0xEF40 15
  admwr $devID 0xEF41 $value1  
  admwr $devID 0xEF40 0x8002
  
  ### Setting Indirect Configuration B Register ###
  # TREF = 975 cycles
  # TRAS_MIN = 6 cycles  
  Poll_BUSY_Bit $devID 0xEF40 15
  admwr $devID 0xEF41 0x3CF6 
  admwr $devID 0xEF40 0x8004

  ### Setting Indirect Configuration C Register ###    
  Poll_BUSY_Bit $devID 0xEF40 15
  admwr $devID 0xEF41 0x3A8E 
  admwr $devID 0xEF40 0x8006
  
  ### Setting Indirect Configuration D Register ###
  # TRFC = 10 cycles
  # TMRD = 2 cycles
  # TERMS = 2 cycles
  # TRP = 3 cycles
  # TRC = 9 cycles  
  Poll_BUSY_Bit $devID 0xEF40 15
  admwr $devID 0xEF41 0x5539 
  admwr $devID 0xEF40 0x8008
 
  ### Setting Indirect Configuration E Register ###
  # TDLL = 200 cycles  
  Poll_BUSY_Bit $devID 0xEF40 15
  admwr $devID 0xEF41 0xC800
  admwr $devID 0xEF40 0x800A
  
  ### Setting Indirect Configuration F Register ###
  # TINIT = 25000 cycles  
  Poll_BUSY_Bit $devID 0xEF40 15  
  admwr $devID 0xEF41 0x61A8
  admwr $devID 0xEF40 0x800C
  
  ### Setting Indirect Configuration G Register ###
  # Use this for 1x32 bit RAM
  # COLUMN_SIZE = 8
  Poll_BUSY_Bit $devID 0xEF40 15
  admwr $devID 0xEF41 0x0200
  admwr $devID 0xEF40 0x800E
  
  # Use this for 2x 16 bit RAM  
  # COLUMN_SIZE = 9
  #Poll_BUSY_Bit $devID 0xEF40 15
  #admwr $devID 0xEF41 0x0400
  #admwr $devID 0xEF40 0x800E
  
  ### Setting Indirect Configuration H Register ###
  # TWTR = 2 cycles  
  # INITAREF = 2
  # APREBIT = 8
  # Use this only for 32 bit RAM
  Poll_BUSY_Bit $devID 0xEF40 15  
  admwr $devID 0xEF41 0x2C28
  admwr $devID 0xEF40 0x8010
    
  # Use this only for 2x 16 bit RAM
  # TWTR = 2 cycles  
  # INITAREF = 2
  # APREBIT = 10
  # Poll_BUSY_Bit $devID 0xEF40 15  
  # admwr $devID 0xEF41 0x2C2A 
  # admwr $devID 0xEF40 0x8010 
  
  ### Setting Indirect Configuration I Register ###
  # ENCONCAP = 1  
  if {$caslat == 0} {
    # CAS Latency is 2 cycles
    set value2 0x8110
  } elseif {$caslat == 1} {
    # CAS Latency is 2.5 cycles
    set value2 0x8114
  } elseif {$caslat == 2} {
    # CAS Latency is 3 cycles
    set value2 0x8118
  }  
    
  Poll_BUSY_Bit $devID 0xEF40 15    
  admwr $devID 0xEF41 $value2
  admwr $devID 0xEF40 0x8012
  
  ### Setting Indirect Configuration S Register ###
  Poll_BUSY_Bit $devID 0xEF40 15  
  admwr $devID 0xEF41 0xC060  
  admwr $devID 0xEF40 0x8080
  
  ### Setting Indirect Reserved Register 1 ###
  Poll_BUSY_Bit $devID 0xEF40 15    
  admwr $devID 0xEF41 0x0F1E 
  admwr $devID 0xEF40 0x8082
  
  ### Setting Indirect Reserved Register 2 ###
  Poll_BUSY_Bit $devID 0xEF40 15    
  admwr $devID 0xEF41 0x0F1E 
  admwr $devID 0xEF40 0x8084
  
  ### Setting Indirect Reserved Register 3 ###
  Poll_BUSY_Bit $devID 0xEF40 15
  admwr $devID 0xEF41 0x0018
  admwr $devID 0xEF40 0x8102
  
  ### Setting RESERVED_1 bit to 1 ###
  admwr $devID 0xEF42 0x0005
  admwr $devID 0xEF43 0x0003    
  
  ### Setting Indirect Configuration Main Register ###  
  # Set RESERVED_1 to 1 and ST to 1
  Poll_BUSY_Bit $devID 0xEF40 15
  admwr $devID 0xEF41 0x8001
  admwr $devID 0xEF40 0x8000
  Poll_BUSY_Bit_H $devID 0xEF42 6  
  
  # Center DDR Interface FIFO   
  admwr $devID 0xE021 0x2
}

#------------------------------------------------------------------------------
# SCRIPT NAME:	EOS_IBUF_Config
#
# DESCRIPTION:	This procedure configures 
#		
# PARAMETERS:   devID - This parameter is used to specify the device 
#                       under configuration
#               channel - 0 (port 1), 1 (port 2), ...  7 (port 8)  
#               fe_geb - 1 (FE mode), 0 (GE mode)
#               crc_check_en_ch - CRC checking enable: 0-off, 1-on
#               ibuf8_critcal_en_ch - Buffer level flow control: 0-off, 1-on
#               insert_length_ch - length insertion: 0-off, 1-on
#               ihft_ch - high threshold for flow control (0 to 1FFFH)
#               ilft_ch - low threshold for flow control (0 to 1FFFFH)
#               cut_thru_ch - cut through level (0x20 or 0x28)
#               ext_fifo_max_depth_ch - maximum external FIFO depth (0 to 100H)
#
# NOTES: The following are recommended settings:
#        1) crc_check_en_ch: set to 1 if Ethernet frame's FCS has not been 
#                            stripped, otherwise set to 0.
#        2) ibuf8_critcal_en: set to 1 for pause flow control based on buffer 
#                             fill level, otherwise set to 0.
#        3) insert_length: set to 1 for GFP operation, otherwise set to 0.
#        4) ihft_ch: default value is 1D60H (470k byte)
#        5) ilft_ch: default value is 1CC0H (460k byte)
#        6) cut_thru_ch: set to 0x28 when Ethernet channel is mapped to a 
#                        STS-3c or VC-4, otherwise set to 0x20.
#        7) ext_fifo_max_depth_ch: default value is 100H (512k byte) 
#
#------------------------------------------------------------------------------

proc EOS_IBUF_Config {devID channel fe_geb crc_check_en_ch ibuf8_critcal_en_ch 
                      insert_length_ch ihft_ch ilft_ch cut_thru_ch 
                      ext_fifo_max_depth_ch} {    
  
  source /usr/lib/cgi-bin/apps/tclscripts/PM5337_util.tcl  
  
  ### Declaring register address ###
  set addr_0xEB1A [dec2hex [expr 0xEB1A + ($channel*0x1)]]	;# 0xB1A +0x1*N
  set addr_0xEB22 [dec2hex [expr 0xEB22 + ($channel*0x1)]]	;# 0xB22 +0x1*N  
  set addr_0xEB2A [dec2hex [expr 0xEB2A + ($channel*0x1)]]	;# 0xB2A +0x1*N  
  set addr_0xEB32 [dec2hex [expr 0xEB32 + ($channel*0x1)]]	;# 0xB32 +0x1*N
  set addr_0xEB3A [dec2hex [expr 0xEB3A + ($channel*0x1)]]	;# 0xB3A +0x1*N  
  
  ### 1. Setting IBUF8 Configuration & Channel Configuration ###                
  # Mapping bit to proper position  
  set value1 [expr 0x4000 | [expr $fe_geb << 15]|[expr $crc_check_en_ch << 4]| \
             [expr $ibuf8_critcal_en_ch << 3]|[expr $insert_length_ch << 2]]
  
  admwr $devID $addr_0xEB1A $value1
  
  ### 2. Setting IBUF8 Channel High Flag Threshold ###
  admwr $devID $addr_0xEB22 $ihft_ch
  
  ### 3. Setting IBUF8 Channel Low Flag Threshold ###
  admwr $devID $addr_0xEB2A $ilft_ch
  
  ### 4. Setting IBUF8 Channel Cut Thru Threshold ###
  admwr $devID $addr_0xEB32 $cut_thru_ch
  
  ### 5. Setting IBUF8 Channel External FIFO Max Depth ###
  admwr $devID $addr_0xEB3A $ext_fifo_max_depth_ch
  
  ### 6. Enable IBUF8 ###
  # Setting IBUF8_EN_CH to 1
  admwrb $devID $addr_0xEB1A 0 1
  
}

#------------------------------------------------------------------------------
# SCRIPT NAME:	EOS_EBUF_Config
#
# DESCRIPTION:	This procedure configures 
#		
# PARAMETERS:   devID - This parameter is used to specify the device 
#                       under configuration
#               channel - 0 (port 1), 1 (port 2), ...  7 (port 8)  
#               
# NOTES: 
#
#------------------------------------------------------------------------------

proc EOS_EBUF_Config {devID channel} {
    
  source /usr/lib/cgi-bin/apps/tclscripts/PM5337_util.tcl    
    
  ### Declaring register address ###
  set addr_0xE91B [dec2hex [expr 0xE91B + ($channel*0x1)]]	;# 0x91B +0x1*N
  set addr_0xE924 [dec2hex [expr 0xE924 + ($channel*0x1)]]	;# 0x924 +0x1*N  
  
  ### 1. Setting EBUF8 Reserved Register ###
  admwr $devID $addr_0xE924 0x0158
  
  ### 2. Enabling EBUF8 ###
  # Setting and Reserved_1 and EBUF8_EN to 1
  admwrb $devID $addr_0xE91B 1 1
  admwrb $devID $addr_0xE91B 2 1
  admwrb $devID $addr_0xE91B 0 1
}

#------------------------------------------------------------------------------
# SCRIPT NAME:	EOS_Encap_Config
#
# DESCRIPTION:	This procedure configures 
#		
# PARAMETERS:   devID - This parameter is used to specify the device 
#                       under configuration
#               channel - 0 (port 1), 1 (port 2), ...  7 (port 8)  
#               mode - 0 (GFP frame-mapped), 1 (HDLC-like)
#               scrmbl - payload scrambling and descrambling: 0-off, 1-on               
#               pfcs_ins - payload FCS insertion and checking : 0-off, 1-on
#               pfcs_mode - 0 (CRC-16), 1 (CRC-32)
#
# NOTES: The following settings are recommended for GFP mode:
#        1) scrmbl = 1
#        2) pfcs_mode = 1 when pfcs_ins = 1
#
#------------------------------------------------------------------------------
proc EOS_Encap_Config {devID channel mode scrmbl pfcs_ins pfcs_mode} {
  
  source /usr/lib/cgi-bin/apps/tclscripts/PM5337_util.tcl  
  
  #########################################################################
  #####                 Configuring TXDP Block                        #####
  #########################################################################
  
  ##### 1. Enable TXDP Block #####
  admwr $devID 0xE700 0x0001
  
  ##### 2. Setting TXDP Indirect Channel Common and Specific Config Register #####  
  ### 2.1 Defining and writing to common configuration register data value ###
  if {$mode == 0} {
    # Recommended GFP Settings     
    set scrmbl 1	;# ensure payload scrambling is enabled
    set data_rev_bit 0
    set pfcs_rev_obyte 0
    set pfcs_rev_obit 0
    set pfcs_rev_ibit 0
    set pfcs_crpt_inv 1
    set pfcs_inv 1
    set pfcs_mode 1	;# ensure FCS calculated using CRC-32
    set chan_en 1
  } elseif {$mode == 1} {
    # Recommened HDLC-Like Settings
    set data_rev_bit 0
    set pfcs_rev_obyte 0
    set pfcs_rev_obit 1
    set pfcs_rev_ibit 1
    set pfcs_crpt_inv 1
    set pfcs_inv 1