pm5337_pdh.tcl

用于EOS芯片的驱动程序, 供参考 参考

  
  # Setup EC1 LIU
  TDKSetMode 1 $intf
    
  #########################################################################  
  ##### Configuring top level bit to process the proper payload types #####
  #########################################################################
  set addr_0xC040 [expr 0xC040 + $intf*0x20]
  
  set addr_0xC458 [expr 0xC458 + $intf*0x100]
  set addr_0xC45C [expr 0xC45C + $intf*0x100]
    
  if {$mode == 0} {
    # Bypass VTPA by setting LO_BYPASS to 1
    admwrb $devID $addr_0xC040 16 1        
  } 
  
  if {$mode == 1 || $mode == 2} {
    # Go through VTPA by setting LO_BYPASS to 0
    admwrb $devID $addr_0xC040 16 0
    
    # Set H4 to bypassed through RTAL and TTAL
    admwrb $devID $addr_0xC458 6 1
    admwrb $devID $addr_0xC45C 6 1
  }
  
  ####################################################
  ##### DS3/E3/EC1 Slice Top Level Configuration #####
  ####################################################
  set addr_0xC0A0 [expr 0xC0A0 + $intf*0x10]    
  
  ### i) Configure Serial Interface ###   
  # - See UNI, DEC1DE3_RISEEN and AEC1DE3_RISEEN in register 0xC0A0.
  #   The default settings are:
  #   - Bipolar mode
  #   - Signals are generated and sampled at falling edge.  
  
  ### ii) Configure EC1/DE3 Slice for EC1 ###
  # Set TU3_AU3B to 0
  admwrb $devID $addr_0xC0A0 18 0
  
  # Set EC1DE3_SRC to 0 for EC1 mode
  admwrb $devID $addr_0xC0A0 7 0
  
  # Set EC1 to unipolar mode
  if {$intf == 0} {
    admwrb 0 0xc0a0 6 1
    wr adm 0xc401 0x1
    wr adm 0xc402 0x1
  }
  if {$intf == 1} {
    admwrb 0 0xc0b0 6 1
    wr adm 0xc501 0x1
    wr adm 0xc502 0x1
  }
  if {$intf == 2} {
    admwrb 0 0xc0c0 6 1 
    wr adm 0xc601 0x1
    wr adm 0xc602 0x1
  }
             
  #############################################
  ##### AJAT, DJAT and DCUS Configuration #####
  #############################################
  # TBD - AJAT and DJAT are bypassed
      
  #############################################################################  
  ##### Configuring VTPI TimeSlot 1, 5, or 9 for the proper payload types #####
  #############################################################################  
  
  # The VTPI Timeslots 1-5-9 are used for processing EC1 traffic with VT/TU in
  # the add direction.
  
  if {$mode == 1} {  
  ### Configuring VTPI Timeslot 1, 5, or 9 for VT1.5  ###
  
    set stm1_ind 0x1
    
    if {$intf == 0} {    
      set tug3_ind 0x1		;# Timeslot 1
    } elseif {$intf == 1} {
      set tug3_ind 0x2		;# Timeslot 5
    } elseif {$intf == 2} {
      set tug3_ind 0x3		;# Timeslot 9
    }
    
    for {set tug2_ind 0x1} {$tug2_ind <= 0x7} {incr tug2_ind} {
      #for {set tu_ind 0x1} {$tu_ind <= 0x4} {incr tu_ind} {
        # Ensure Busy Bit is low
        Poll_BUSY_Bit $devID 0xC280 15
      
        # Set CONFIG[1:0] to 11b for VT-1.5
        admwr $devID 0xC281 0x00001800
      
        # Trigger Indirect Access
        set iaddr_value [expr [expr $stm1_ind << 8]|[expr $tug3_ind << 6]|[expr $tug2_ind << 3]|0x1]
        admwr $devID 0xC280 $iaddr_value
     #}
    }        
  }
  
  if {$mode == 2} {  
  
  ### Configuring VTPI Timeslot 1, 5, or 9 for VT2  ###
  
    set stm1_ind 0x1
        
    if {$intf == 0} {    
      set tug3_ind 0x1		;# Timeslot 1
    } elseif {$intf == 1} {
      set tug3_ind 0x2		;# Timeslot 5
    } elseif {$intf == 2} {
      set tug3_ind 0x3		;# Timeslot 9
    }
    
    for {set tug2_ind 0x1} {$tug2_ind <= 0x7} {incr tug2_ind} {
      #for {set tu_ind 0x1} {$tu_ind <= 0x3} {incr tu_ind} {
        # Ensure Busy Bit is low
        Poll_BUSY_Bit $devID 0xC280 15
      
        # Set CONFIG[1:0] to 10b for VT-2
        admwr $devID 0xC281 0x00001000
      
        # Trigger Indirect Access
        set iaddr_value [expr [expr $stm1_ind << 8]|[expr $tug3_ind << 6]|[expr $tug2_ind << 3]|0x1]
        admwr $devID 0xC280 $iaddr_value
      #}
    }        
  }  
 
  ############################################################################  
  ##### Configuring VTPA Timeslot #1,5 or 9 for the proper payload types #####
  ############################################################################  
  
  if {$mode == 1} {  
  ### Configuring VTPA Timeslot 1, 5, or 9 for VT1.5  ###
  
    set stm1_ind 0x1
    
    if {$intf == 0} {    
      set tug3_ind 0x1		;# Timeslot 1
    } elseif {$intf == 1} {
      set tug3_ind 0x2		;# Timeslot 5
    } elseif {$intf == 2} {
      set tug3_ind 0x3		;# Timeslot 9
    }
    
    for {set tug2_ind 0x1} {$tug2_ind <= 0x7} {incr tug2_ind} {
      #for {set tu_ind 0x1} {$tu_ind <= 0x4} {incr tu_ind} {
        # Ensure Busy Bit is low
        Poll_BUSY_Bit $devID 0xC180 15
      
        # Set CONFIG[1:0] to 11b for VT-1.5
        admwr $devID 0xC181 0x00000600
      
        # Trigger Indirect Access
        set iaddr_value [expr [expr $stm1_ind << 8]|[expr $tug3_ind << 6]|[expr $tug2_ind << 3]|0x1]
        admwr $devID 0xC180 $iaddr_value
      #}
    }        
  }
  
  if {$mode == 2} {  
  
  ### Configuring VTPA Timeslot 1, 5, or 9 for VT2  ###
  
    set stm1_ind 0x1
    
    if {$intf == 0} {    
      set tug3_ind 0x1		;# Timeslot 1
    } elseif {$intf == 1} {
      set tug3_ind 0x2		;# Timeslot 5
    } elseif {$intf == 2} {
      set tug3_ind 0x3		;# Timeslot 9
    }
    
    for {set tug2_ind 0x1} {$tug2_ind <= 0x7} {incr tug2_ind} {
      #for {set tu_ind 0x1} {$tu_ind <= 0x3} {incr tu_ind} {
        # Ensure Busy Bit is low
        Poll_BUSY_Bit $devID 0xC180 15
      
        # Set CONFIG[1:0] to 10b for VT-2
        admwr $devID 0xC181 0x00000500
      
        # Trigger Indirect Access
        set iaddr_value [expr [expr $stm1_ind << 8]|[expr $tug3_ind << 6]|[expr $tug2_ind << 3]|0x1]
        admwr $devID 0xC180 $iaddr_value
      #}
    }
  }
}

#------------------------------------------------------------------------------
# SCRIPT NAME:	PDH_DS3_E3_Config
#
# DESCRIPTION:	This script configure the DS3 or E3 interface in the PDH  
#		subsystem.
#		
# PARAMETERS:   devID - This parameter is used to specify the device 
#                       under configuration
#               
#               intf - 0 (port 1), 1 (port 2), 2 (port 3)
#
#               mode - Valid values are 0 to 5.  See notes for details.
#
#               ds3_framing - 0 (unframed), 1 (M13), 2(Cbit)
#
#               e3_framing - 0 (unframed), 1 (G.751), 2 (G.832)
#
# NOTES:	
#        1)  Mode    PDH           SONET/SDH                 Timeslot
#          -------------------------------------------------------------------
#            0      DS3      <----->  AU3/VC3/C3             2, 6, or 10
#            1      DS3      <----->  AU4/TUG3/TU3/VC3/C3    3, 7, or 11
#            2      DS3/DS1  <----->  AU3/VC3/C3             2, 6, or 10
#            3      DS3/DS1  <----->  AU4/TUG3/TU3/VC3/C3    3, 7, or 11
#            4      E3       <----->  AU3/VC3/C3             2, 6, or 10
#            5      E3       <----->  AU4/TUG3/TU3/VC3/C3    3, 7, or 11
#
#        2) The DS3 FRMR and TRAN blocks are set to C-Bit parity operation 
#           mode by default.
#
#        3) The E3 FRMR and TRAN blocks are set to G.751 format by default.
#           The code needs to be modified for G.832 mode.
#
#        4) In mode 2 and 3, the DS1/E1 interface is setup to use the SBI-TR
#           bus. The DS1 framer is bypassed (FRMR_DE1 and TRAN_DE1), and the DS1 
#           is pass through the interface unmodified.
#  
#  REVISION HISTORY:
#  Released 2 - Added the line 'admwrb $devID 0xc003 7 1' for mode 1 and 5
#             - Removed repeated lines
#
#------------------------------------------------------------------------------
proc PDH_DS3_E3_Config {devID intf mode {ds3_framing 0} {e3_framing 0}} {

  source /usr/lib/cgi-bin/apps/tclscripts/PM5337_util.tcl  
  
  # Define register address
  set addr_0xC0A0 [expr 0xC0A0 + $intf*0x10]  
  set addr_0xC701 [expr 0xC701 + $intf*0x100]    
  set addr_0xC720 [expr 0xC720 + $intf*0x100]   
  set addr_0xC730 [expr 0xC730 + $intf*0x100]
  set addr_0xC734 [expr 0xC734 + $intf*0x100]     
  set addr_0xC704 [expr 0xC704 + $intf*0x100] 
  set addr_0xC707 [expr 0xC707 + $intf*0x100]  
  set addr_0xC740 [expr 0xC740 + $intf*0x100]           
  set addr_0xC7A0 [expr 0xC7A0 + $intf*0x100]
  set addr_0xC799 [expr 0xC799 + $intf*0x100]  
  set addr_0xC798 [expr 0xC798 + $intf*0x100]
  set addr_0xC790 [expr 0xC790 + $intf*0x100]  
  set addr_0xC750 [expr 0xC750 + $intf*0x100]  
  set addr_0xC702 [expr 0xC702 + $intf*0x100]
  set addr_0xC749 [expr 0xC749 + $intf*0x100]
  set addr_0xC751 [expr 0xC751 + $intf*0x100]
  set addr_0xC7A1 [expr 0xC7A1 + $intf*0x100]             
  set addr_0xC748 [expr 0xC748 + $intf*0x100]  
  set addr_0xC750 [expr 0xC750 + $intf*0x100]              
  set addr_0xC748 [expr 0xC748 + $intf*0x100]
  set addr_0xC794 [expr 0xC794 + $intf*0x100]
  set addr_0xC744 [expr 0xC744 + $intf*0x100] 

  ### FPGA Reference Clock Setup  
  if {$mode == 0x4 || $mode == 0x5} {
    ### FPGA setup - E3 clock setup ###
    set init_value [expr [rd fpga 0x7] & 0x1E7F]
    set value [expr $init_value | 0x1 << 7]; #shift by 8 if U17 is populated, shift by 7 if U18 is populated
    set value [dec2hex $value] 
    wr fpga 0x7 $value      
  } else {           
    
    ### FPGA DS3 reference clock Setup ###
    set init_value [rd fpga 0x7]
    set value [expr $init_value | 0x1 << 7]
    set value [dec2hex $value] 
    wr fpga 0x7 $value     
  }
            
  ################################################################
  ##### ADM 622 Device and Subsystem Top Level Configuration #####
  ################################################################            
  ### i) Configure Serial Interface ###     
  # Configure interface to unipolar mode
  admwrb $devID $addr_0xC0A0 6 1 
      
  ### ii) Configure EC1/DE3 Slice to specify if the traffic is ###
  ###     AU3 or TU3, and E3 or DS3                            ###
    
  if {$mode == 0 || $mode == 2} {  
    # Set TU3_AU3B to 0, EC1DE3_SRC to 1, and E3DS3B to 0 for
    # AU3 with DS3
    admwrb $devID $addr_0xC0A0 18 0
    admwrb $devID $addr_0xC0A0 7 1
    admwrb $devID $addr_0xC0A0 3 0
  } elseif {$mode == 1 || $mode == 3} {  
    # Set TU3_AU3B to 1, EC1DE3_SRC to 1, and E3DS3B to 0 for
    # AU4 with DS3
    admwrb $devID $addr_0xC0A0 18 1
    admwrb $devID $addr_0xC0A0 7 1
    admwrb $devID $addr_0xC0A0 3 0
  } elseif {$mode == 4} {       
    # Set TU3_AU3B to 0, EC1DE3_SRC to 1, and E3DS3B to 1 for
    # AU3 with E3
    admwrb $devID $addr_0xC0A0 18 0
    admwrb $devID $addr_0xC0A0 7 1
    admwrb $devID $addr_0xC0A0 3 1
  } elseif {$mode == 5} {    
    # Set TU3_AU3B to 1, EC1DE3_SRC to 1, and E3DS3B to 1 for
    # AU4 with E3
    admwrb $devID $addr_0xC0A0 18 1
    admwrb $devID $addr_0xC0A0 7 1
    admwrb $devID $addr_0xC0A0 3 1
  }
  
  ### Set THPPPDH_TU3 for mode 1 and 5 ###  
  # Added in Released 2
  if {$mode == 1 || $mode == 5} {
    admwrb $devID 0xC003 7 1
  }      
    
  ### iii) Setup DS1 Interface for Mode 2 and 3 Only ###        
  if {$mode == 2 || $mode == 3} {
    # Set DS1 interface to SBI-TR mode
    # Set DS1 interface to route to the M13 block      
    PDH_DS1_E1_Config $devID 0 0 1
  } 
      
  ### iv) Specify which DE3 Slice is used for M13/M13 multiplexing ###
  ### for Mode 2 and 3 Only                                        ###    
  if {$mode == 2 || $mode == 3} {
    if {$intf == 0} {
      # Set M13 DS3 source is from slice 1
      admwrb $devID 0xC003 9 0
      admwrb $devID 0xC003 8 0
    } elseif {$intf == 1} {
      # Set M13 DS3 source is from slice 2
      admwrb $devID 0xC003 9 0
      admwrb $devID 0xC003 8 1
    } elseif {$intf == 2} {
      # Set M13 DS3 source is from slice 3
      admwrb $devID 0xC003 9 1
      admwrb $devID 0xC003 8 0
    }
  }