i2c-algo-ibm_ocp.c

I2C总线LINUX驱动程序

              if(timeout < 0) {
	         // Error Handler
		 //printk(KERN_ERR "Error: read timed out\n");
                 return rdcount;
	      }
              //printk(KERN_DEBUG "--->Got interrupt\n");

              ret = analyze_status(adap, &error_code);
	      if(ret < 0) {
                 if(error_code == IIC_ERR_INCOMPLETE_XFR)
                    return rdcount;
                 else
                    return error_code;
              }

	      for(j=0; j<4; j++) {
                 // Wait for data to shuffle to top of data buffer
                 // This value needs to optimized.
		 udelay(1);
	         buf[rdcount] = iic_inb(adap, iic->mdbuf);
	         rdcount++;
		 //printk(KERN_DEBUG "--->Read one byte\n");
              }
           }
	}

	else if((loops >= 1) && (remainder > 0)){
	//printk(KERN_DEBUG "iic_readbytes: (loops >=1) && (remainder > 0)\n");
	   for(i=0; i<loops; i++) {
              //
              // Issue command to begin master read (4 bytes maximum)
              //
              //printk(KERN_DEBUG "--->Issued read command\n");
              iic_outb(adap, iic->cntl, 0x37);
              //
              // Wait for transmission to complete.  When it does,
              // loop to the top of the for statement and write the
              // next four bytes.
              //
              //printk(KERN_DEBUG "--->Waiting for interrupt\n");
              timeout = wait_for_pin(adap, &status);
              if(timeout < 0) {
                 // Error Handler
                 //printk(KERN_ERR "Error: read timed out\n");
                 return rdcount;
              }
              //printk(KERN_DEBUG "--->Got interrupt\n");

              ret = analyze_status(adap, &error_code);
              if(ret < 0) {
                 if(error_code == IIC_ERR_INCOMPLETE_XFR)
                    return rdcount;
                 else
                    return error_code;
              }

              for(j=0; j<4; j++) {
                 // Wait for data to shuffle to top of data buffer
                 // This value needs to optimized.
                 udelay(1);
                 buf[rdcount] = iic_inb(adap, iic->mdbuf);
                 rdcount++;
                 //printk(KERN_DEBUG "--->Read one byte\n");
              }
           }
        }

	//printk(KERN_DEBUG "iic_readbytes: expedite read\n");
	if(remainder == 0) remainder = 4;
	DEB2(printk(KERN_DEBUG "iic_readbytes: writing %x to IICO_CNTL\n", (0x03 | ((remainder-1) << 4))));

	if(xfer_type == IIC_COMBINED_XFER) {
	   iic_outb(adap, iic->cntl, (0x0b | ((remainder-1) << 4)));
        }
        else {
	   iic_outb(adap, iic->cntl, (0x03 | ((remainder-1) << 4)));
        }
	DEB2(printk(KERN_DEBUG "iic_readbytes: Wait for pin\n"));
        timeout = wait_for_pin(adap, &status);
	DEB2(printk(KERN_DEBUG "iic_readbytes: Got the interrupt\n"));
        if(timeout < 0) {
           // Error Handler
	   //printk(KERN_ERR "Error: read timed out\n");
           return rdcount;
        }

        ret = analyze_status(adap, &error_code);
        if(ret < 0) {
           if(error_code == IIC_ERR_INCOMPLETE_XFR)
              return rdcount;
           else
              return error_code;
        }

	//printk(KERN_DEBUG "iic_readbyte: Begin reading data buffer\n");
	for(i=0; i<remainder; i++) {
	   buf[rdcount] = iic_inb(adap, iic->mdbuf);
	   // printk(KERN_DEBUG "iic_readbytes:  Character read = %x\n", buf[rdcount]);
           rdcount++;
	}

	return rdcount;
}


//
// Description:  This function implements combined transactions.  Combined
// transactions consist of combinations of reading and writing blocks of data.
// Each transfer (i.e. a read or a write) is separated by a repeated start
// condition.
//
static int iic_combined_transaction(struct i2c_adapter *i2c_adap, struct i2c_msg msgs[], int num) 
{
   int i;
   struct i2c_msg *pmsg;
   int ret;

   DEB2(printk(KERN_DEBUG "Beginning combined transaction\n"));
	for(i=0; i < num; i++) {
		pmsg = &msgs[i];
		if(pmsg->flags & I2C_M_RD) {

			// Last read or write segment needs to be terminated with a stop
			if(i < num-1) {
				DEB2(printk(KERN_DEBUG "This one is a read\n"));
			}
			else {
				DEB2(printk(KERN_DEBUG "Doing the last read\n"));
			}
			ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, (i < num-1) ? IIC_COMBINED_XFER : IIC_SINGLE_XFER);

			if (ret != pmsg->len) {
				DEB2(printk("i2c-algo-ppc405.o: fail: "
							"only read %d bytes.\n",ret));
				return i;
			}
			else {
				DEB2(printk("i2c-algo-ppc405.o: read %d bytes.\n",ret));
			}
		}
		else if(!(pmsg->flags & I2C_M_RD)) {

			// Last read or write segment needs to be terminated with a stop
			if(i < num-1) {
				DEB2(printk(KERN_DEBUG "This one is a write\n"));
			}
			else {
				DEB2(printk(KERN_DEBUG "Doing the last write\n"));
			}
			ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, (i < num-1) ? IIC_COMBINED_XFER : IIC_SINGLE_XFER);

			if (ret != pmsg->len) {
				DEB2(printk("i2c-algo-ppc405.o: fail: "
							"only wrote %d bytes.\n",ret));
				return i;
			}
			else {
				DEB2(printk("i2c-algo-ppc405.o: wrote %d bytes.\n",ret));
			}
		}
	}
 
	return num;
}


//
// Description: Whenever we initiate a transaction, the first byte clocked
// onto the bus after the start condition is the address (7 bit) of the
// device we want to talk to.  This function manipulates the address specified
// so that it makes sense to the hardware when written to the IIC peripheral.
//
// Note: 10 bit addresses are not supported in this driver, although they are
// supported by the hardware.  This functionality needs to be implemented.
//
static inline int iic_doAddress(struct i2c_algo_iic_data *adap,
                                struct i2c_msg *msg, int retries) 
{
	struct iic_regs *iic;
	unsigned short flags = msg->flags;
	unsigned char addr;
	struct iic_ibm *adap_priv_data = adap->data;
	iic = (struct iic_regs *) adap_priv_data->iic_base;

//
// The following segment for 10 bit addresses needs to be ported
//
/* Ten bit addresses not supported right now
	if ( (flags & I2C_M_TEN)  ) { 
		// a ten bit address
		addr = 0xf0 | (( msg->addr >> 7) & 0x03);
		DEB2(printk(KERN_DEBUG "addr0: %d\n",addr));
		// try extended address code...
		ret = try_address(adap, addr, retries);
		if (ret!=1) {
			printk(KERN_ERR "iic_doAddress: died at extended address code.\n");
			return -EREMOTEIO;
		}
		// the remaining 8 bit address
		iic_outb(adap,msg->addr & 0x7f);
		// Status check comes here
		if (ret != 1) {
			printk(KERN_ERR "iic_doAddress: died at 2nd address code.\n");
			return -EREMOTEIO;
		}
		if ( flags & I2C_M_RD ) {
			i2c_repstart(adap);
			// okay, now switch into reading mode
			addr |= 0x01;
			ret = try_address(adap, addr, retries);
			if (ret!=1) {
				printk(KERN_ERR "iic_doAddress: died at extended address code.\n");
				return -EREMOTEIO;
			}
		}
	} else ----------> // normal 7 bit address

Ten bit addresses not supported yet */

	addr = ( msg->addr << 1 );
	if (flags & I2C_M_RD )
		addr |= 1;
	if (flags & I2C_M_REV_DIR_ADDR )
		addr ^= 1;
	//
	// Write to the low slave address
	//
	iic_outb(adap, iic->lmadr, addr);
	//
	// Write zero to the high slave register since we are
	// only using 7 bit addresses
	//
	iic_outb(adap, iic->hmadr, 0);

	return 0;
}


//
// Description: Prepares the controller for a transaction (clearing status
// registers, data buffers, etc), and then calls either iic_readbytes or
// iic_sendbytes to do the actual transaction.
//
static int iic_xfer(struct i2c_adapter *i2c_adap,
		    struct i2c_msg msgs[], 
		    int num)
{
	struct iic_regs *iic;
	struct i2c_algo_iic_data *adap = i2c_adap->algo_data;
	struct iic_ibm *adap_priv_data = adap->data;
	struct i2c_msg *pmsg;
	int i = 0;
	int ret;
	iic = (struct iic_regs *) adap_priv_data->iic_base;

	pmsg = &msgs[i];

	//
	// Clear status register
	//
	DEB2(printk(KERN_DEBUG "iic_xfer: iic_xfer: Clearing status register\n"));
	iic_outb(adap, iic->sts, 0x0a);

	//
	// Wait for any pending transfers to complete
	//
	DEB2(printk(KERN_DEBUG "iic_xfer: Waiting for any pending transfers to complete\n"));
	while((ret = iic_inb(adap, iic->sts)) == 0x01) {
		;
	}

	//
	// Flush master data buf
	//
	DEB2(printk(KERN_DEBUG "iic_xfer: Clearing master data buffer\n"));		
	ret = iic_inb(adap, iic->mdcntl);
	iic_outb(adap, iic->mdcntl, ret | 0x40);

	//
	// Load slave address
	//
	DEB2(printk(KERN_DEBUG "iic_xfer: Loading slave address\n"));
	ret = iic_doAddress(adap, pmsg, i2c_adap->retries);

        //
        // Check to see if the bus is busy
        //
        ret = iic_inb(adap, iic->extsts);
        // Mask off the irrelevant bits
        ret = ret & 0x70;
        // When the bus is free, the BCS bits in the EXTSTS register are 0b100
        if(ret != 0x40) return IIC_ERR_LOST_ARB;

	//
	// Combined transaction (read and write)
	//
	if(num > 1) {
           DEB2(printk(KERN_DEBUG "iic_xfer: Call combined transaction\n"));
           ret = iic_combined_transaction(i2c_adap, msgs, num);
        }
	//
	// Read only
	//
	else if((num == 1) && (pmsg->flags & I2C_M_RD)) {
	   //
	   // Tell device to begin reading data from the  master data 
	   //
	   DEB2(printk(KERN_DEBUG "iic_xfer: Call adapter's read\n"));
	   ret = iic_readbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
	} 
        //
	// Write only
	//
	else if((num == 1 ) && (!(pmsg->flags & I2C_M_RD))) {
	   //
	   // Write data to master data buffers and tell our device
	   // to begin transmitting
	   //
	   DEB2(printk(KERN_DEBUG "iic_xfer: Call adapter's write\n"));
	   ret = iic_sendbytes(i2c_adap, pmsg->buf, pmsg->len, IIC_SINGLE_XFER);
	}	

	return ret;   
}


//
// Description: Implements device specific ioctls.  Higher level ioctls can
// be found in i2c-core.c and are typical of any i2c controller (specifying
// slave address, timeouts, etc).  These ioctls take advantage of any hardware
// features built into the controller for which this algorithm-adapter set
// was written.  These ioctls allow you to take control of the data and clock
// lines on the IBM PPC 405 IIC controller and set the either high or low,
// similar to a GPIO pin.
//
static int algo_control(struct i2c_adapter *adapter, 
	unsigned int cmd, unsigned long arg)
{
	struct iic_regs *iic;
	struct i2c_algo_iic_data *adap = adapter->algo_data;
	struct iic_ibm *adap_priv_data = adap->data;
	int ret=0;
	int lines;
	iic = (struct iic_regs *) adap_priv_data->iic_base;

	lines = iic_inb(adap, iic->directcntl);

	if (cmd == IICO_I2C_SDAHIGH) {
	      lines = lines & 0x01;
	      if( lines ) lines = 0x04;
	      else lines = 0;
	      iic_outb(adap, iic->directcntl,(0x08|lines));
	}
	else if (cmd == IICO_I2C_SDALOW) {
	      lines = lines & 0x01;
	      if( lines ) lines = 0x04;
              else lines = 0;
              iic_outb(adap, iic->directcntl,(0x00|lines));
	}
	else if (cmd == IICO_I2C_SCLHIGH) {
              lines = lines & 0x02;
              if( lines ) lines = 0x08;
              else lines = 0;
              iic_outb(adap, iic->directcntl,(0x04|lines));
	}
	else if (cmd == IICO_I2C_SCLLOW) {
              lines = lines & 0x02;
	      if( lines ) lines = 0x08;
              else lines = 0;
              iic_outb(adap, iic->directcntl,(0x00|lines));
	}
	else if (cmd == IICO_I2C_LINEREAD) {
	      ret = lines;
	}
	return ret;
}


static u32 iic_func(struct i2c_adapter *adap)
{
	return I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR | 
	       I2C_FUNC_PROTOCOL_MANGLING; 
}


/* -----exported algorithm data: -------------------------------------	*/

static struct i2c_algorithm iic_algo = {
	.name		= "IBM on-chip IIC algorithm",
	.id		= I2C_ALGO_OCP,
	.master_xfer	= iic_xfer,
	.algo_control	= algo_control,
	.functionality	= iic_func,
};

/* 
 * registering functions to load algorithms at runtime 
 */


//
// Description: Register bus structure
//
int i2c_ocp_add_bus(struct i2c_adapter *adap)
{
	struct i2c_algo_iic_data *iic_adap = adap->algo_data;

	DEB2(printk(KERN_DEBUG "i2c-algo-iic.o: hw routines for %s registered.\n",
	            adap->name));

	/* register new adapter to i2c module... */

	adap->id |= iic_algo.id;
	adap->algo = &iic_algo;

	adap->timeout = 100;	/* default values, should	*/
	adap->retries = 3;		/* be replaced by defines	*/

	iic_init(iic_adap);
	i2c_add_adapter(adap);
	return 0;
}


//
// Done
//
int i2c_ocp_del_bus(struct i2c_adapter *adap)
{
	return i2c_del_adapter(adap);
}


EXPORT_SYMBOL(i2c_ocp_add_bus);
EXPORT_SYMBOL(i2c_ocp_del_bus);

//
// The MODULE_* macros resolve to nothing if MODULES is not defined
// when this file is compiled.
//
MODULE_AUTHOR("MontaVista Software <www.mvista.com>");
MODULE_DESCRIPTION("PPC 405 iic algorithm");
MODULE_LICENSE("GPL");

MODULE_PARM(i2c_debug,"i");

MODULE_PARM_DESC(i2c_debug,
        "debug level - 0 off; 1 normal; 2,3 more verbose; 9 iic-protocol");