📄 ide.h
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/******************************************************************
本程序只供学习使用，未经作者许可，不得用于其它任何用途
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IDE.H File IDE address and command
Created by Computer-lov
Date: 2005.3.12
Edit date:2006.3.2
Version V1.1
Copyright(C) Computer-lov 2005-2015
All rigths reserved
*******************************************************************/
#ifndef __IDE_H__
#define __IDE_H__
void reset_IDE(void);
void read_IDE_16(unsigned char);
void write_IDE_16(unsigned char);
unsigned char read_IDE_8(unsigned char);
void write_IDE_8(unsigned char,unsigned char);
void read_IDE_data(void);
void write_IDE_data(void);
void read_IDE_status(void);
void read_IDE_error(void);
unsigned char wait_IDE_busy(void);
void write_IDE_command(unsigned char);
void soft_reset_IDE(void);
void get_IDE_infromation(void);
void write_IDE_LBA0(unsigned char);
void write_IDE_LBA1(unsigned char);
void write_IDE_LBA2(unsigned char);
void write_IDE_LBA3(unsigned char);
void write_IDE_sector_count(unsigned char);
void read_IDE_buffer(void);
void write_IDE_buffer(void);
void read_IDE_sector(void);
void write_IDE_sector(void);
void IDE_initial(void);
void system_initial(void);
extern unsigned char IDE_Buffer_L,IDE_Buffer_H;
extern unsigned char DISK_CAPACITY[8];
#define set_IDE_address() IDE_ALE=1;IDE_ALE=0;
/* TABLE 6-1: INTERFACE SIGNALS
+----------------------------------+ +-----------+
| HOST I/O | | DRIVE I/O |
| CONNECTOR | | CONNECTOR |
| | | |
| HOST RESET 1 | ----- RESET- -------->| 1 |
| 2 | ----- Ground -------- | 2 |
| HOST DATA BUS BIT 7 3 |<----- DD7 ----------->| 3 |
| HOST DATA BUS BIT 8 4 |<----- DD8 ----------->| 4 |
| HOST DATA BUS BIT 6 5 |<----- DD6 ----------->| 5 |
| HOST DATA BUS BIT 9 6 |<----- DD9 ----------->| 6 |
| HOST DATA BUS BIT 5 7 |<----- DD5 ----------->| 7 |
| HOST DATA BUS BIT 10 8 |<----- DD10 ---------->| 8 |
| HOST DATA BUS BIT 4 9 |<----- DD4 ----------->| 9 |
| HOST DATA BUS BIT 11 10 |<----- DD11 ---------->| 10 |
| HOST DATA BUS BIT 3 11 |<----- DD3 ----------->| 11 |
| HOST DATA BUS BIT 12 12 |<----- DD12 ---------->| 12 |
| HOST DATA BUS BIT 2 13 |<----- DD2 ----------->| 13 |
| HOST DATA BUS BIT 13 14 |<----- DD13 ---------->| 14 |
| HOST DATA BUS BIT 1 15 |<----- DD1 ----------->| 15 |
| HOST DATA BUS BIT 14 16 |<----- DD14 ---------->| 16 |
| HOST DATA BUS BIT 0 17 |<----- DD0 ----------->| 17 |
| HOST DATA BUS BIT 15 18 |<----- DD15 ---------->| 18 |
| 19 | ----- Ground -------- | 19 |
| 20 | ----- (keypin) ------ | 20 |
| DMA REQUEST 21 |<----- DMARQ --------- | 21 |
| 22 | ----- Ground -------- | 22 |
| HOST I/O WRITE 23 | ----- DIOW- --------->| 23 |
| 24 | ----- Ground -------- | 24 |
| HOST I/O READ 25 | ----- DIOR- --------->| 25 |
| 26 | ----- Ground -------- | 26 |
| I/O CHANNEL READY 27 |<----- IORDY --------- | 27 |
| SPINDLE SYNC or CABLE SELECT 28 |*---- SPSYNC:CSEL -----*| 28 |
| DMA ACKNOWLEDGE 29 | ----- DMACK- -------->| 29 |
| 30 | ----- Ground -------- | 30 |
| HOST INTERRUPT REQUEST 31 |<----- INTRQ --------- | 31 |
| HOST 16 BIT I/O 32 |<----- IOCS16- ------- | 32 |
| HOST ADDRESS BUS BIT 1 33 | ----- DA1 ----------->| 33 |
| PASSED DIAGNOSTICS 34 |*----- PDIAG- --------*| 34 |
| HOST ADDRESS BUS BIT 0 35 | ----- DAO ----------->| 35 |
| HOST ADDRESS BUS BIT 2 36 | ----- DA2 ----------->| 36 |
| HOST CHIP SELECT 0 37 | ----- CS1FX- -------->| 37 |
| HOST CHIP SELECT 1 38 | ----- CS3FX- -------->| 38 |
| DRIVE ACTIVE/DRIVE 1 PRESENT 39 |<----- DASP- ---------*| 39 |
| 40 | ----- Ground -------- | 40 |
+----------------------------------+ +-----------+
* Drive Intercommunication Signals
*/
/*
DATA BUS 0-7 <====> P1
DATA BUS 8-16 <====> P2
IORDY ---->P34
ALE <-----P33
DIOW <-----P36
DIOR <-----P37
*/
#include <at89X52.h>
#define IDE_DATA_L P1
#define IDE_DATA_H P2
#define IDE_IORDY P3_4
#define IDE_DIOW P3_0
#define IDE_DIOR P3_1
#define IDE_ALE P3_3
/*
Logic conventions are: A = signal asserted
N = signal negated
x = does not matter which it is
TABLE 7-1: I/O PORT FUNCTIONS/SELECTION ADDRESSES
+-------------------------------+-----------------------------------------+
| Addresses | Functions |
|CS1FX-|CS3FX-| DA2 | DA1 | DA0 | READ (DIOR-) | WRITE (DIOW-) |
+------+------+-----+-----+-----+---------------------+-------------------+
| Control Block Registers |
+------+------+-----+-----+-----+---------------------+-------------------+
| N | N | x | x | x | Data Bus High Imped | Not used |
| N | A | 0 | x | X | Data Bus High Imped | Not used |
| N | A | 1 | 0 | x | Data Bus High Imped | Not used |
| N | A | 1 | 1 | 0 | Alternate Status | Device Control |
| N | A | 1 | 1 | 1 | Drive Address | Not used |
+------+------+-----+-----+-----+---------------------+-------------------+
| Command Block Registers |
+------+------+-----+-----+-----+---------------------+-------------------+
| A | N | 0 | 0 | 0 | Data | Data |
| A | N | 0 | 0 | 1 | Error Register | Features |
| A | N | 0 | 1 | 0 | Sector Count | Sector Count |
| A | N | 0 | 1 | 1 | Sector Number | Sector Number |
| A | N | 0 | 1 | 1 | * LBA Bits 0- 7 | * LBA Bits 0- 7 |
| A | N | 1 | 0 | 0 | Cylinder Low | Cylinder Low |
| A | N | 1 | 0 | 0 | * LBA Bits 8-15 | * LBA Bits 8-15 |
| A | N | 1 | 0 | 1 | Cylinder High | Cylinder High |
| A | N | 1 | 0 | 1 | * LBA Bits 16-23 | * LBA Bits 16-23 |
| A | N | 1 | 1 | 0 | Drive/Head | Drive/Head |
| A | N | 1 | 1 | 0 | * LBA Bits 24-27 | * LBA Bits 24-27 |
| A | N | 1 | 1 | 1 | Status | Command |
| A | A | x | x | x | Invalid Address | Invalid Address |
+------+------+-----+-----+-----+---------------------+-------------------+
* Mapping of registers in LBA Mode
*/
/*
DA0 -----> P10
DA1 -----> P11
DA3 -----> P12
CS1FX -----> P13
CS3FX -----> P14
CSEL -----> P15
RESET -----> P17
*/
#define IDE_Address P1
/*
#define IDE_Bus_Not_Use 0x00
#define IDE_Alternate_Status 0x16
#define IDE_Device_Control 0x16
#define IDE_Drive_Address 0x17
#define IDE_Data 0x08
#define IDE_Error_Register 0x09
#define IDE_Features 0x09
#define IDE_Sector_Count 0x0A
#define IDE_Sector_Nuber 0x0B
#define IDE_LBA_Bits_0_7 0x0B
#define IDE_Cylinder_Low 0x0C
#define IDE_LBA_Bits_8_15 0x0C
#define IDE_Cylinder_High 0x0D
#define IDE_LBA_Bits_16_23 0x0D
#define IDE_Drive_Head 0x0E
#define IDE_LBA_Bits_24_27 0x0E
#define IDE_Status 0x0F
#define IDE_Command 0x0F
#define IDE_Reset 0x80
*/
#define IDE_Bus_Not_Use 0x98
#define IDE_Alternate_Status 0x8E
#define IDE_Device_Control 0x8E
#define IDE_Drive_Address 0x8F
#define IDE_Data 0x90
#define IDE_Error_Register 0x91
#define IDE_Features 0x91
#define IDE_Sector_Count 0x92
#define IDE_Sector_Nuber 0x93
#define IDE_LBA_Bits_0_7 0x93
#define IDE_Cylinder_Low 0x94
#define IDE_LBA_Bits_8_15 0x94
#define IDE_Cylinder_High 0x95
#define IDE_LBA_Bits_16_23 0x95
#define IDE_Drive_Head 0x96
#define IDE_LBA_Bits_24_27 0x96
#define IDE_Status 0x97
#define IDE_Command 0x97
#define IDE_Reset 0x18
/*
Alternate Status Register
7 6 5 4 3 2 1 0
+-------+-------+-------+-------+-------+-------+-------+-------+
| BSY | DRDY | DWF | DSC | DRQ | CORR | IDX | ERR |
+-------+-------+-------+-------+-------+-------+-------+-------+
*/
/*
7.2.2 Command Register
This register contains the command code being sent to the drive. Command
execution begins immediately after this register is written. The executable
commands, the command codes, and the necessary parameters for each command are
listed in Table 9-1.
*/
/*
7.2.3 Cylinder High Register
This register contains the high order bits of the starting cylinder address
for any disk access. At the end of the command, this register is updated to
reflect the current cylinder number. The most significant bits of the cylinder
address shall be loaded into the cylinder high Register.
In LBA Mode this register contains Bits 16-23. At the end of the command, this
register is updated to reflect the current LBA Bits 16-23.
NOTE: Prior to the introduction of this standard, only the lower 2 bits of
this register were valid, limiting cylinder address to 10 bits i.e.
1,024 cylinders.
*/
/*
7.2.4 Cylinder Low Register
This register contains the low order 8 bits of the starting cylinder address
for any disk access. At the end of the command, this register is updated to
reflect the current cylinder number.
In LBA Mode this register contains Bits 8-15. At the end of the command, this
register is updated to reflect the current LBA Bits 8-15.
7.2.5 Data Register
This 16-bit register is used to transfer data blocks between the device data
buffer and the host. It is also the register through which sector information
is transferred on a Format Track command. Data transfers may be either PIO or
DMA.
*/
/*
7.2.6 Device Control Register
The bits in this register are as follows:
7 6 5 4 3 2 1 0
+-------+-------+-------+-------+-------+-------+-------+-------+
| x | x | x | x | 1 | SRST | nIEN | 0 |
+-------+-------+-------+-------+-------+-------+-------+-------+
- SRST is the host software reset bit. The drive is held reset when this bit
is set. If two disk drives are daisy chained on the interface, this bit
resets both simultaneously. Drive 1 is not required to execute the DASP-
handshake procedure.
- nIEN is the enable bit for the drive interrupt to the host. When nIEN=0,
and the drive is selected, INTRQ shall be enabled through a tri-state
buffer. When nIEN=1, or the drive is not selected, the INTRQ signal shall
be in a high impedance state.
*/
/*
7.2.7 Drive Address Register
This register contains the inverted drive select and head select addresses of
the currently selected drive. The bits in this register are as follows:
7 6 5 4 3 2 1 0
+-------+-------+-------+-------+-------+-------+-------+-------+
| HiZ | nWTG | nHS3 | nHS2 | nHS1 | nHS0 | nDS1 | nDS0 |
+-------+-------+-------+-------+-------+-------+-------+-------+
- HiZ shall always be in a high impedance state.
- nWTG is the Write Gate bit. When writing to the disk drive is in progress,
nWTG=0.
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