c2407_reg_c.h

ucosII在TMS320LF2407成功移植的源代码

#define  EVAIFRA 		(unsigned int *)0x742F	/* Group A Interrupt Flag Register*/
#define  EVAIFRB 		(unsigned int *)0x7430	/* Group B Interrupt Flag Register*/
#define  EVAIFRC 		(unsigned int *)0x7431	/* Group C Interrupt Flag Register*/

/* Event Manager B (EVB) registers*/

#define  GPTCONB 		(unsigned int *)0x7500	/* GP Timer control register B */
#define  T3CNT 			(unsigned int *)0x7501	/* GP Timer 3 counter register */
#define  T3CMPR 		(unsigned int *)0x7502	/* GP Timer 3 compare register */
#define  T3PR 			(unsigned int *)0x7503	/* GP Timer 3 period register */
#define  T3CON 			(unsigned int *)0x7504	/* GP Timer 3 control register*/
#define  T4CNT 			(unsigned int *)0x7505	/* GP Timer 4 counter register */
#define  T4CMPR 		(unsigned int *)0x7506	/* GP Timer 4 compare register*/
#define  T4PR 			(unsigned int *)0x7507	/* GP Timer 4 period register*/
#define  T4CON 			(unsigned int *)0x7508	/* GP Timer 4 control register*/

#define  COMCONB 		(unsigned int *)0x7511	/* Compare control register B */
#define  ACTRB 			(unsigned int *)0x7513	/* Full compare Action control register B*/
#define  DBTCONB 		(unsigned int *)0x7515	/* Dead朾and timer control register B*/

#define  CMPR4 			(unsigned int *)0x7517	/* Full compare unit compare register4*/
#define  CMPR5 			(unsigned int *)0x7518	/* Full compare unit compare register5*/
#define  CMPR6 			(unsigned int *)0x7519	/* Full compare unit compare register6*/

#define  CAPCONB 		(unsigned int *)0x7520	/* Capture control register B*/
#define  CAPFIFOB 		(unsigned int *)0x7522	/* Capture FIFO status register B */

#define  CAP4FIFO 		(unsigned int *)0x7523	/* Capture Channel 4 FIFO Top*/
#define  CAP5FIFO 		(unsigned int *)0x7524	/* Capture Channel 5 FIFO Top*/
#define  CAP6FIFO 		(unsigned int *)0x7525	/* Capture Channel 6 FIFO Top */

#define  CAP4FBOT 		(unsigned int *)0x7527	/* Bottom reg. of capture FIFO stack 4 */
#define  CAP5FBOT 		(unsigned int *)0x7527	/* Bottom reg. of capture FIFO stack 5*/
#define  CAP6FBOT 		(unsigned int *)0x7527	/* Bottom reg. of capture FIFO stack 6*/

#define  EVBIMRA 		(unsigned int *)0x752C	/* Group A Interrupt Mask Register */
#define  EVBIMRB 		(unsigned int *)0x752D	/* Group B Interrupt Mask Register */
#define  EVBIMRC 		(unsigned int *)0x752E	/* Group C Interrupt Mask Register */

#define  EVBIFRA 		(unsigned int *)0x752F	/* Group A Interrupt Flag Register*/
#define  EVBIFRB 		(unsigned int *)0x7530	/* Group B Interrupt Flag Register*/
#define  EVBIFRC 		(unsigned int *)0x7531	/* Group C Interrupt Flag Register*/

/* CAN registers*/

#define  CANMDER 		(unsigned int *)0x7100	/* CAN Mailbox Direction/Enable register*/
#define  CANTCR 		(unsigned int *)0x7101	/* CAN Transmission Control register*/
#define  CANRCR 		(unsigned int *)0x7102	/* CAN Recieve Control register */
#define  CANMCR 		(unsigned int *)0x7103	/* CAN Master Control register */
#define  CANBCR2 		(int *)0x7104	/* CAN Bit Config register 2 */
#define  CANBCR1 		(unsigned int *)0x7105	/* CAN Bit Config register 1*/
#define  CANESR 		(unsigned int *)0x7106	/* CAN Error Status register*/
#define  CANGSR 		(unsigned int *)0x7107	/* CAN Global Status register*/
#define  CANCEC 		(unsigned int *)0x7108	/* CAN Trans and Rcv Err counters */
#define  CANIFR 		(unsigned int *)0x7109	/* CAN Interrupt Flag Register*/
#define  CANIMR 		(unsigned int *)0x710a	/* CAN Interrupt Mask Register */
#define  CANLAM0H 		(unsigned int *)0x710b	/* CAN Local Acceptance Mask MBX0/1 */
#define  CANLAM0L 		(unsigned int *)0x710c	/* CAN Local Acceptance Mask MBX0/1*/
#define  CANLAM1H 		(unsigned int *)0x710d	/* CAN Local Acceptance Mask MBX2/3 */
#define  CANLAM1L 		(unsigned int *)0x710e	/* CAN Local Acceptance Mask MBX2/3*/

#define  CANMSGID0L 	(unsigned int *)0x7200	/* CAN Message ID for mailbox 0 (lower 16 bits)*/
#define  CANMSGID0H 	(unsigned int *)0x7201	/* CAN Message ID for mailbox 0 (upper 16 bits)*/
#define  CANMSGCTRL0 	(unsigned int *)0x7202	/* CAN RTR and DLC*/
#define  CANMBX0A 		(unsigned int *)0x7204	/* CAN 2 of 8 bytes of Mailbox 0*/
#define  CANMBX0B 		(unsigned int *)0x7205	/* CAN 2 of 8 bytes of Mailbox 0*/
#define  CANMBX0C 		(unsigned int *)0x7206	/* CAN 2 of 8 bytes of Mailbox 0 */
#define  CANMBX0D 		(unsigned int *)0x7207	/* CAN 2 of 8 bytes of Mailbox 0 */

#define  CANMSGID1L 	(unsigned int *)0x7208	/* CAN Message ID for mailbox 1 (lower 16 bits)*/
#define  CANMSGID1H 	(unsigned int *)0x7209	/* CAN Message ID for mailbox 1 (upper 16 bits)*/
#define  CANMSGCTRL1 	(unsigned int *)0x720A	/* CAN RTR and DLC*/
#define  CANMBX1A 		(unsigned int *)0x720C	/* CAN 2 of 8 bytes of Mailbox 1*/
#define  CANMBX1B 		(unsigned int *)0x720D	/* CAN 2 of 8 bytes of Mailbox 1*/
#define  CANMBX1C 		(unsigned int *)0x720E	/* CAN 2 of 8 bytes of Mailbox 1*/
#define  CANMBX1D 		(unsigned int *)0x720F	/* CAN 2 of 8 bytes of Mailbox 1*/

#define  CANMSGID2L 	(unsigned int *)0x7210	/* CAN Message ID for mailbox 2 (lower 16 bits)*/
#define  CANMSGID2H 	(unsigned int *)0x7211	/* CAN Message ID for mailbox 2 (upper 16 bits)*/
#define  CANMSGCTRL2 	(unsigned int *)0x7212	/* CAN RTR and DLC */
#define  CANMBX2A		(unsigned int *)0x7214	/* CAN 2 of 8 bytes of Mailbox 2*/
#define  CANMBX2B 		(unsigned int *)0x7215	/* CAN 2 of 8 bytes of Mailbox 2*/
#define  CANMBX2C 		(unsigned int *)0x7216	/* CAN 2 of 8 bytes of Mailbox 2*/
#define  CANMBX2D 		(unsigned int *)0x7217	/* CAN 2 of 8 bytes of Mailbox 2*/

#define  CANMSGID3L 	(unsigned int *)0x7218	/* CAN Message ID for mailbox 3 (lower 16 bits)*/
#define  CANMSGID3H 	(unsigned int *)0x7219	/* CAN Message ID for mailbox 3 (upper 16 bits)*/
#define  CANMSGCTRL3 	(unsigned int *)0x721A	/* CAN RTR and DLC*/
#define  CANMBX3A 		(unsigned int *)0x721C	/* CAN 2 of 8 bytes of Mailbox 3 */
#define  CANMBX3B 		(unsigned int *)0x721D	/* CAN 2 of 8 bytes of Mailbox 3 */
#define  CANMBX3C 		(unsigned int *)0x721E	/* CAN 2 of 8 bytes of Mailbox 3*/
#define  CANMBX3D 		(unsigned int *)0x721F	/* CAN 2 of 8 bytes of Mailbox 3 */

#define  CANMSGID4L 	(unsigned int *)0x7220	/* CAN Message ID for mailbox 4 (lower 16 bits)*/
#define  CANMSGID4H 	(unsigned int *)0x7221	/* CAN Message ID for mailbox 4 (upper 16 bits)*/
#define  CANMSGCTRL4 	(unsigned int *)0x7222	/* CAN RTR and DLC*/
#define  CANMBX4A 		(unsigned int *)0x7224	/* CAN 2 of 8 bytes of Mailbox 4*/
#define  CANMBX4B 		(unsigned int *)0x7225	/* CAN 2 of 8 bytes of Mailbox 4*/
#define  CANMBX4C 		(unsigned int *)0x7226	/* CAN 2 of 8 bytes of Mailbox 4*/
#define  CANMBX4D 		(unsigned int *)0x7227	/* CAN 2 of 8 bytes of Mailbox 4*/

#define  CANMSGID5L 	(unsigned int *)0x7228	/* CAN Message ID for mailbox 5 (lower 16 bits)*/
#define  CANMSGID5H 	(unsigned int *)0x7229	/* CAN Message ID for mailbox 5 (upper 16 bits)*/
#define  CANMSGCTRL5 	(unsigned int *)0x722A	/* CAN RTR and DLC*/
#define  CANMBX5A 		(unsigned int *)0x722C	/* CAN 2 of 8 bytes of Mailbox 5 */
#define  CANMBX5B 		(unsigned int *)0x722D	/* CAN 2 of 8 bytes of Mailbox 5 */
#define  CANMBX5C 		(unsigned int *)0x722E	/* CAN 2 of 8 bytes of Mailbox 5 */
#define  CANMBX5D 		(unsigned int *)0x722F	/* CAN 2 of 8 bytes of Mailbox 5 */

/*--------------------------------------------------- */
/*I/O space mapped registers  */
/*--------------------------------------------------- */

#define  WSGR 		(unsigned int *)0x0FFFF	/* Wait朣tate Generator Control register */
#define  FCMR 		(unsigned int *)0x0FF0F	/* Flash control mode register */

/*--------------------------------------------------- */
/*Bit codes for Test bit instruction (BIT) (15 Loads bit 0 into TC)*/
/*---------------------------------------------------*/
#define BIT15 		  0x0000	/* Bit Code for 15*/
#define BIT14 		  0x0001	/* Bit Code for 14*/
#define BIT13 		  0x0002	/* Bit Code for 13*/
#define BIT12 		  0x0003	/* Bit Code for 12*/
#define BIT11 		  0x0004	/* Bit Code for 11*/
#define BIT10 		  0x0005	/* Bit Code for 10 */
#define BIT9 		  0x0006	/* Bit Code for 9 */
#define BIT8 		  0x0007	/* Bit Code for 8 */
#define BIT7 		  0x0008	/* Bit Code for 7 */
#define BIT6 		  0x0009	/* Bit Code for 6 */
#define BIT5 		  0x000A	/* Bit Code for 5*/
#define BIT4 		  0x000B	/* Bit Code for 4 */
#define BIT3 		  0x000C	/* Bit Code for 3 */
#define BIT2 		  0x000D	/* Bit Code for 2*/
#define BIT1 		  0x000E	/* Bit Code for 1*/
#define BIT0 		  0x000F	/* Bit Code for 0*/
                                                                   
#endif