📄 adsp-bf533-ez-kit.c
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#include "ADSP-BF533-Ez-kit.h"
//--------------------------------------------------------------------------//
// Function: Init_EBIU //
// //
// Description: This function initialises and enables asynchronous memory //
// banks in External Bus Interface Unit so that Flash A can be //
// accessed. //
//--------------------------------------------------------------------------//
void Init_EBIU(void)
{
*pEBIU_AMBCTL0 = 0x7bb07bb0;
*pEBIU_AMBCTL1 = 0x7bb07bb0;
*pEBIU_AMGCTL = 0x000f;
}
//--------------------------------------------------------------------------//
// Function: Init_Flash //
// //
// Description: This function initialises pin direction of Port A in Flash A//
// to output. The AD1836_RESET on the ADSP-BF533 EZ-KIT board //
// is connected to Port A. //
//--------------------------------------------------------------------------//
void Init_Flash(void)
{
*pFlashA_PortA_Dir = 0x1;
}
void Init_SDRAM(void)
{
/* Check whether SDRAM is enabled already. If so, return.
If not, continue with configurations. */
if (!(*pEBIU_SDSTAT & 0x8)) return;
//SDRAM Refresh Rate Control Register
*pEBIU_SDRRC = 0x0817;
//SDRAM Memory Bank Control Register
*pEBIU_SDBCTL= 0x0013;
//SDRAM Memory Global Control Register
*pEBIU_SDGCTL= 0x0091998d;
}
USHORT Setup_Blackfin(void)
{
USHORT err = 0;
//asm("r0 = 0x30; SYSCFG = r0;");
ssync();
Init_EBIU();
Init_Flash();
return err;
}
void Setup_ADP7171()
{
unsigned long *flashA_Ptr = (unsigned long *) flashA_csio;
// Initialize flash A csio regs (port A and B).
flashA_Ptr[portA_data_out] = 0;
ssync();
// Set direction control registers.
flashA_Ptr[portA_data_dir] = 0xFFFF;
ssync();
//De-assert reset from ADP7171 device (flashA portA bit 2)
flashA_Ptr[portA_data_out] |= RST_7171;
}
void Setup_PPI()
{
*pPPI_CONTROL = PORT_DIR;
ssync();
}
void Enable_PPI()
{
*pPPI_CONTROL |= 1;
ssync();
}
void Setup_VideoFrame_DMA( unsigned char * frame_start, unsigned short X_pels, unsigned short Y_pels)
{
//DMA0_START_ADDR
*pDMA0_START_ADDR = frame_start;
//DMA0_CONFIG
*pDMA0_CONFIG = 0x1090;
//DMA0_X_COUNT
*pDMA0_X_COUNT = X_pels; // 0x06B4;
//DMA0_X_MODIFY
*pDMA0_X_MODIFY = 0x0001;
//DMA0_Y_COUNT
*pDMA0_Y_COUNT = Y_pels; // 0x020D
//DMA0_Y_MODIFY
*pDMA0_Y_MODIFY = 0x0001;
}
void Enable_VideoFrame_DMA()
{
//Enable DMA
*pDMA0_CONFIG |= 1;
ssync();
}
/******************************************************************************
AD1836 Support
*****************************************************************************/
short AD1836_Block_0_L[AUDIO_BLOCK_SIZE];
short AD1836_Block_1_L[AUDIO_BLOCK_SIZE];
short AD1836_Block_0_R[AUDIO_BLOCK_SIZE];
short AD1836_Block_1_R[AUDIO_BLOCK_SIZE];
short * AD1836_Block_L = AD1836_Block_1_L;
short * AD1836_Block_R = AD1836_Block_1_R;
USHORT AD1836_db_ptr = 0;
USHORT AD1836_which_buffer = 0;
bool AD1836_buffer_ready = false;
volatile short sCodec1836TxRegs[CODEC_1836_REGS_LENGTH] =
{
DAC_CONTROL_1 | 0x000,
DAC_CONTROL_2 | 0x000,
DAC_VOLUME_0 | 0x3ff,
DAC_VOLUME_1 | 0x3ff,
DAC_VOLUME_2 | 0x3ff,
DAC_VOLUME_3 | 0x3ff,
DAC_VOLUME_4 | 0x000,
DAC_VOLUME_5 | 0x000,
ADC_CONTROL_1 | 0x000,
ADC_CONTROL_2 | 0x000,
ADC_CONTROL_3 | 0x000
};
// SPORT0 DMA transmit buffer
volatile int iTxBuffer1[4];
// SPORT0 DMA receive buffer
volatile int iRxBuffer1[4];
EX_INTERRUPT_HANDLER(AD1836_Sample_Block_Manager)
{
// confirm interrupt handling
*pDMA1_IRQ_STATUS = 0x0001;
if (AD1836_which_buffer)
{
iTxBuffer1[INTERNAL_DAC_L0] = ((int) AD1836_Block_0_L[AD1836_db_ptr])<<7;
iTxBuffer1[INTERNAL_DAC_L1] = ((int) AD1836_Block_0_L[AD1836_db_ptr])<<7;
iTxBuffer1[INTERNAL_DAC_R0] = ((int) AD1836_Block_0_R[AD1836_db_ptr])<<7;
iTxBuffer1[INTERNAL_DAC_R1] = ((int) AD1836_Block_0_R[AD1836_db_ptr])<<7;
AD1836_Block_0_L[AD1836_db_ptr] = (short) (iRxBuffer1[INTERNAL_ADC_L0]>>7);
AD1836_Block_0_R[AD1836_db_ptr] = (short) (iRxBuffer1[INTERNAL_ADC_R0]>>7);
AD1836_Block_L = AD1836_Block_1_L;
AD1836_Block_R = AD1836_Block_1_R;
}
else
{
iTxBuffer1[INTERNAL_DAC_L0] = ((int) AD1836_Block_1_L[AD1836_db_ptr])<<7;
iTxBuffer1[INTERNAL_DAC_L1] = ((int) AD1836_Block_1_L[AD1836_db_ptr])<<7;
iTxBuffer1[INTERNAL_DAC_R0] = ((int) AD1836_Block_1_R[AD1836_db_ptr])<<7;
iTxBuffer1[INTERNAL_DAC_R1] = ((int) AD1836_Block_1_R[AD1836_db_ptr])<<7;
AD1836_Block_1_L[AD1836_db_ptr] = (short) (iRxBuffer1[INTERNAL_ADC_L0]>>7);
AD1836_Block_1_R[AD1836_db_ptr] = (short) (iRxBuffer1[INTERNAL_ADC_R0]>>7);
AD1836_Block_L = AD1836_Block_0_L;
AD1836_Block_R = AD1836_Block_0_R;
}
AD1836_db_ptr++;
if (AD1836_db_ptr >= AUDIO_BLOCK_SIZE)
{
AD1836_db_ptr = 0;
AD1836_which_buffer = !AD1836_which_buffer;
AD1836_buffer_ready = true;
asm("raise 12;");
}
}
void(*AD1836_User_Function)(short*,short*);
EX_INTERRUPT_HANDLER(AD1836_Block_Function)
{
AD1836_User_Function(AD1836_Block_L, AD1836_Block_R);
}
//--------------------------------------------------------------------------//
// Function: Init1836() //
// //
// Description: This function sets up the SPI port to configure the AD1836. //
// The content of the array sCodec1836TxRegs is sent to the //
// codec. //
//--------------------------------------------------------------------------//
void Init1836(void)
{
int i;
int j;
static unsigned char ucActive_LED = 0x01;
// write to Port A to reset AD1836
*pFlashA_PortA_Data = 0x00;
// write to Port A to enable AD1836
*pFlashA_PortA_Data = ucActive_LED;
// wait to recover from reset
for (i=0; i<0xf000; i++);
// Enable PF4
*pSPI_FLG = FLS4;
// Set baud rate SCK = HCLK/(2*SPIBAUD) SCK = 2MHz
*pSPI_BAUD = 16;
// configure spi port
// SPI DMA write, 16-bit data, MSB first, SPI Master
*pSPI_CTL = TIMOD_DMA_TX | SIZE | MSTR;
// Set up DMA5 to transmit
// Map DMA5 to SPI
*pDMA5_PERIPHERAL_MAP = 0x5000;
// Configure DMA5
// 16-bit transfers
*pDMA5_CONFIG = WDSIZE_16;
// Start address of data buffer
*pDMA5_START_ADDR = sCodec1836TxRegs;
// DMA inner loop count
*pDMA5_X_COUNT = CODEC_1836_REGS_LENGTH;
// Inner loop address increment
*pDMA5_X_MODIFY = 2;
// enable DMAs
*pDMA5_CONFIG = (*pDMA5_CONFIG | DMAEN);
// enable spi
*pSPI_CTL = (*pSPI_CTL | SPE);
// wait until dma transfers for spi are finished
for (j=0; j<0xaff; j++);
// disable spi
*pSPI_CTL = 0x0000;
}
//--------------------------------------------------------------------------//
// Function: Init_Sport0 //
// //
// Description: Configure Sport0 for I2S mode, to transmit/receive data //
// to/from the AD1836. Configure Sport for external clocks and //
// framesyncs. //
//--------------------------------------------------------------------------//
void Init_Sport0(void)
{
// Sport0 receive configuration
// External CLK, External Frame sync, MSB first, Active Low, Late frame
// 24-bit data, Stereo frame sync enable
*pSPORT0_RCR1 = RFSR | LRFS | LARFS | RCKFE;
*pSPORT0_RCR2 = SLEN_24 | RXSE | RSFSE;
// Sport0 transmit configuration
// External CLK, External Frame sync, MSB first, Active Low, Late frame
// 24-bit data, Secondary side enable, Stereo frame sync enable
*pSPORT0_TCR1 = TFSR | LTFS | LATFS | TCKFE;
*pSPORT0_TCR2 = SLEN_24 | TXSE | TSFSE;
}
//--------------------------------------------------------------------------//
// Function: Init_DMA_SPORT0 //
// //
// Description: Initialise DMA1 in autobuffer mode to receive and DMA2 in //
// autobuffer mode to transmit //
//--------------------------------------------------------------------------//
void Init_DMA_SPORT0(void)
{
// Set up DMA1 to receive
// Map DMA1 to Sport0 RX
*pDMA1_PERIPHERAL_MAP = 0x1000;
// Configure DMA1
// 32-bit transfers, Interrupt on completion, Autobuffer mode
*pDMA1_CONFIG = WNR | WDSIZE_32 | DI_EN | FLOW_1;
// Start address of data buffer
*pDMA1_START_ADDR = iRxBuffer1;
// DMA inner loop count
*pDMA1_X_COUNT = 4;
// Inner loop address increment
*pDMA1_X_MODIFY = 4;
// Set up DMA2 to transmit
// Map DMA2 to Sport0 TX
*pDMA2_PERIPHERAL_MAP = 0x2000;
// Configure DMA2
// 32-bit transfers, Autobuffer mode
*pDMA2_CONFIG = WDSIZE_32 | FLOW_1;
// Start address of data buffer
*pDMA2_START_ADDR = iTxBuffer1;
// DMA inner loop count
*pDMA2_X_COUNT = 4;
// Inner loop address increment
*pDMA2_X_MODIFY = 4;
}
//--------------------------------------------------------------------------//
// Function: Enable_DMA_Sport //
// //
// Description: Enable DMA1, DMA2, Sport0 TX and Sport0 RX //
//--------------------------------------------------------------------------//
void Enable_DMA_Sport0(void)
{
// enable DMAs
*pDMA2_CONFIG = (*pDMA2_CONFIG | DMAEN);
*pDMA1_CONFIG = (*pDMA1_CONFIG | DMAEN);
// enable Sport0 TX and RX
*pSPORT0_TCR1 = (*pSPORT0_TCR1 | TSPEN);
*pSPORT0_RCR1 = (*pSPORT0_RCR1 | RSPEN);
}
//--------------------------------------------------------------------------//
// Function: Init_Interrupts //
// //
// Description: Initialise Interrupt for Sport0 RX //
//--------------------------------------------------------------------------//
void Init_Interrupt_SPORT0( void )
{
// Set Sport0 RX (DMA1) interrupt priority to 2 = IVG9
/* *pSIC_IAR0 = 0xffffffff;
*pSIC_IAR1 = 0xffffff2f;
*pSIC_IAR2 = 0xffffffff;
*/
// assign ISRs to interrupt vectors
// Sport0 RX ISR -> IVG 9
register_handler(ik_ivg9, AD1836_Sample_Block_Manager);
register_handler(ik_ivg12,AD1836_Block_Function);
// enable Sport0 RX interrupt
*pSIC_IMASK |= 0x00001200;
}
//--------------------------------------------------------------------------//
// Function: Setup_AD1836 //
// //
// Description: Set up the AD1836 CODEC
//--------------------------------------------------------------------------//
void Setup_AD1836( void(*function)(short *,short *) )
{
AD1836_User_Function = function;
Init1836();
Init_Sport0();
Init_DMA_SPORT0();
Init_Interrupt_SPORT0();
}
//--------------------------------------------------------------------------//
// Function: Open_AD1836 //
// //
// Description: Starts AD1836 DMAs
//--------------------------------------------------------------------------//
void Open_AD1836(void)
{
Enable_DMA_Sport0();
}
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