i2c_timesim.vhd

Xilinx ISE 官方源代码盘第十章

    )
    port map (
      ADR0 => N8933,
      ADR1 => N5934,
      ADR2 => uC_CTRL_mbdr_micro(5),
      ADR3 => N5687,
      O => uC_CTRL_n0039_5_1_O
    );
  uC_CTRL_n0039_4_1 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => N5934,
      ADR1 => uC_CTRL_mbdr_micro(4),
      ADR2 => N5687,
      ADR3 => N8931,
      O => uC_CTRL_n0039_4_1_O
    );
  uC_CTRL_mbdr_micro_5_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => uC_CTRL_mbdr_micro_5_SRMUX_OUTPUTNOT
    );
  uC_CTRL_n0041_2_0 : X_LUT4
    generic map(
      INIT => X"B0F0"
    )
    port map (
      ADR0 => uC_CTRL_prs_state_FFd4,
      ADR1 => N7297,
      ADR2 => uC_CTRL_data_out(2),
      ADR3 => N8991,
      O => uC_CTRL_data_out_2_FROM
    );
  uC_CTRL_n0041_2_73 : X_LUT4
    generic map(
      INIT => X"FFA8"
    )
    port map (
      ADR0 => N8991,
      ADR1 => CHOICE371,
      ADR2 => CHOICE382,
      ADR3 => uC_CTRL_n0041_2_0_O,
      O => uC_CTRL_n0041_2_73_O
    );
  uC_CTRL_data_out_2_XUSED : X_BUF
    port map (
      I => uC_CTRL_data_out_2_FROM,
      O => uC_CTRL_n0041_2_0_O
    );
  uC_CTRL_data_out_2_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => uC_CTRL_data_out_2_SRMUX_OUTPUTNOT
    );
  uC_CTRL_n0041_3_38 : X_LUT4
    generic map(
      INIT => X"AA80"
    )
    port map (
      ADR0 => N8991,
      ADR1 => CHOICE299,
      ADR2 => CHOICE296,
      ADR3 => CHOICE291,
      O => uC_CTRL_data_out_3_FROM
    );
  uC_CTRL_n0041_3_47 : X_LUT4
    generic map(
      INIT => X"FF88"
    )
    port map (
      ADR0 => uC_CTRL_data_out(3),
      ADR1 => N5676,
      ADR2 => VCC,
      ADR3 => uC_CTRL_n0041_3_38_O,
      O => uC_CTRL_n0041_3_47_O
    );
  uC_CTRL_data_out_3_XUSED : X_BUF
    port map (
      I => uC_CTRL_data_out_3_FROM,
      O => uC_CTRL_n0041_3_38_O
    );
  uC_CTRL_data_out_3_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => uC_CTRL_data_out_3_SRMUX_OUTPUTNOT
    );
  Ker56651 : X_LUT4
    generic map(
      INIT => X"EFFF"
    )
    port map (
      ADR0 => r_w_IBUF,
      ADR1 => uC_CTRL_prs_state_FFd4,
      ADR2 => uC_CTRL_cntrl_en,
      ADR3 => uC_CTRL_prs_state_FFd2,
      O => uC_CTRL_men_FROM
    );
  uC_CTRL_n00301 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => N8937,
      ADR1 => uC_CTRL_men,
      ADR2 => N5945,
      ADR3 => N5667,
      O => uC_CTRL_n00301_O
    );
  uC_CTRL_men_XUSED : X_BUF
    port map (
      I => uC_CTRL_men_FROM,
      O => N5667
    );
  uC_CTRL_men_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => uC_CTRL_men_SRMUX_OUTPUTNOT
    );
  uC_CTRL_n0039_7_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => N5934,
      ADR1 => N8937,
      ADR2 => N5687,
      ADR3 => uC_CTRL_mbdr_micro(7),
      O => uC_CTRL_n0039_7_1_O
    );
  uC_CTRL_n0039_6_1 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => N5934,
      ADR1 => uC_CTRL_mbdr_micro(6),
      ADR2 => N5687,
      ADR3 => N8935,
      O => uC_CTRL_n0039_6_1_O
    );
  uC_CTRL_mbdr_micro_7_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => uC_CTRL_mbdr_micro_7_SRMUX_OUTPUTNOT
    );
  uC_CTRL_n0041_4_0 : X_LUT4
    generic map(
      INIT => X"BF00"
    )
    port map (
      ADR0 => uC_CTRL_prs_state_FFd4,
      ADR1 => N8991,
      ADR2 => N7297,
      ADR3 => uC_CTRL_data_out(4),
      O => uC_CTRL_data_out_4_FROM
    );
  uC_CTRL_n0041_4_73 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => CHOICE398,
      ADR1 => N8991,
      ADR2 => CHOICE387,
      ADR3 => uC_CTRL_n0041_4_0_O,
      O => uC_CTRL_n0041_4_73_O
    );
  uC_CTRL_data_out_4_XUSED : X_BUF
    port map (
      I => uC_CTRL_data_out_4_FROM,
      O => uC_CTRL_n0041_4_0_O
    );
  uC_CTRL_data_out_4_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => uC_CTRL_data_out_4_SRMUX_OUTPUTNOT
    );
  I2C_CTRL_scl_state_Out8_SW0 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => I2C_CTRL_scl_state_FFd6,
      ADR3 => I2C_CTRL_scl_state_FFd1,
      O => N6220_FROM
    );
  I2C_CTRL_CLKCNT_n0002_41 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => I2C_CTRL_clk_cnt_rst,
      ADR1 => I2C_CTRL_scl_state_FFd4,
      ADR2 => I2C_CTRL_scl_state_FFd2,
      ADR3 => N6220,
      O => N6220_GROM
    );
  N6220_XUSED : X_BUF
    port map (
      I => N6220_FROM,
      O => N6220
    );
  N6220_YUSED : X_BUF
    port map (
      I => N6220_GROM,
      O => I2C_CTRL_CLKCNT_n0002
    );
  uC_CTRL_data_out_5_FFY_RSTOR : X_OR2
    port map (
      I0 => uC_CTRL_data_out_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => uC_CTRL_data_out_5_FFY_RST
    );
  uC_CTRL_data_out_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => uC_CTRL_n0041_5_73_O,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => uC_CTRL_data_out_5_FFY_RST,
      O => uC_CTRL_data_out(5)
    );
  uC_CTRL_n0041_5_0 : X_LUT4
    generic map(
      INIT => X"8CCC"
    )
    port map (
      ADR0 => uC_CTRL_prs_state_FFd4,
      ADR1 => uC_CTRL_data_out(5),
      ADR2 => N7297,
      ADR3 => N8991,
      O => uC_CTRL_data_out_5_FROM
    );
  uC_CTRL_n0041_5_73 : X_LUT4
    generic map(
      INIT => X"FFE0"
    )
    port map (
      ADR0 => CHOICE414,
      ADR1 => CHOICE403,
      ADR2 => N8991,
      ADR3 => uC_CTRL_n0041_5_0_O,
      O => uC_CTRL_n0041_5_73_O
    );
  uC_CTRL_data_out_5_XUSED : X_BUF
    port map (
      I => uC_CTRL_data_out_5_FROM,
      O => uC_CTRL_n0041_5_0_O
    );
  uC_CTRL_data_out_5_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => uC_CTRL_data_out_5_SRMUX_OUTPUTNOT
    );
  uC_CTRL_data_out_6_FFY_RSTOR : X_OR2
    port map (
      I0 => uC_CTRL_data_out_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => uC_CTRL_data_out_6_FFY_RST
    );
  uC_CTRL_data_out_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => uC_CTRL_n0041_6_73_O,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => uC_CTRL_data_out_6_FFY_RST,
      O => uC_CTRL_data_out(6)
    );
  uC_CTRL_n0041_6_0 : X_LUT4
    generic map(
      INIT => X"CC4C"
    )
    port map (
      ADR0 => N7297,
      ADR1 => uC_CTRL_data_out(6),
      ADR2 => N8991,
      ADR3 => uC_CTRL_prs_state_FFd4,
      O => uC_CTRL_data_out_6_FROM
    );
  uC_CTRL_n0041_6_73 : X_LUT4
    generic map(
      INIT => X"FFA8"
    )
    port map (
      ADR0 => N8991,
      ADR1 => CHOICE435,
      ADR2 => CHOICE446,
      ADR3 => uC_CTRL_n0041_6_0_O,
      O => uC_CTRL_n0041_6_73_O
    );
  uC_CTRL_data_out_6_XUSED : X_BUF
    port map (
      I => uC_CTRL_data_out_6_FROM,
      O => uC_CTRL_n0041_6_0_O
    );
  uC_CTRL_data_out_6_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => uC_CTRL_data_out_6_SRMUX_OUTPUTNOT
    );
  uC_CTRL_data_out_7_FFY_RSTOR : X_OR2
    port map (
      I0 => uC_CTRL_data_out_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => uC_CTRL_data_out_7_FFY_RST
    );
  uC_CTRL_data_out_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => uC_CTRL_n0041_7_73_O,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => GND,
      RST => uC_CTRL_data_out_7_FFY_RST,
      O => uC_CTRL_data_out(7)
    );
  uC_CTRL_n0041_7_0 : X_LUT4
    generic map(
      INIT => X"D0F0"
    )
    port map (
      ADR0 => N8991,
      ADR1 => uC_CTRL_prs_state_FFd4,
      ADR2 => uC_CTRL_data_out(7),
      ADR3 => N7297,
      O => uC_CTRL_data_out_7_FROM
    );
  uC_CTRL_n0041_7_73 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => CHOICE430,
      ADR1 => N8991,
      ADR2 => CHOICE419,
      ADR3 => uC_CTRL_n0041_7_0_O,
      O => uC_CTRL_n0041_7_73_O
    );
  uC_CTRL_data_out_7_XUSED : X_BUF
    port map (
      I => uC_CTRL_data_out_7_FROM,
      O => uC_CTRL_n0041_7_0_O
    );
  uC_CTRL_data_out_7_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => uC_CTRL_data_out_7_SRMUX_OUTPUTNOT
    );
  I2C_CTRL_scl_state_FFd7_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => I2C_CTRL_scl_state_FFd7_SRMUX_OUTPUTNOT,
      O => I2C_CTRL_scl_state_FFd7_FFY_SET
    );
  I2C_CTRL_scl_state_FFd7_42 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => I2C_CTRL_scl_state_FFd7_In48_O,
      CE => VCC,
      CLK => clk_BUFGP,
      SET => I2C_CTRL_scl_state_FFd7_FFY_SET,
      RST => GND,
      O => I2C_CTRL_scl_state_FFd7
    );
  I2C_CTRL_scl_state_FFd7_In48_SW0 : X_LUT4
    generic map(
      INIT => X"FF1D"
    )
    port map (
      ADR0 => CHOICE240,
      ADR1 => I2C_CTRL_CLKCNT_q_int(0),
      ADR2 => I2C_CTRL_scl_state_FFd1,
      ADR3 => I2C_CTRL_CLKCNT_q_int(1),
      O => I2C_CTRL_scl_state_FFd7_FROM
    );
  I2C_CTRL_scl_state_FFd7_In48 : X_LUT4
    gener