hdllib.ref

Xilinx ISE 官方源代码盘第十章

EN i2c_control NULL d:/my_design/example-10-1/i2c/xst/i2c/../../source/i2c_control.vhd sub00/vhpl04
AR i2c behave d:/my_design/example-10-1/i2c/xst/i2c/../../source/i2c.vhd sub00/vhpl09
EN shift8 NULL d:/my_design/example-10-1/i2c/xst/i2c/../../source/shift.vhd sub00/vhpl02
EN i2c NULL d:/my_design/example-10-1/i2c/xst/i2c/../../source/i2c.vhd sub00/vhpl08
AR i2c_control behave d:/my_design/example-10-1/i2c/xst/i2c/../../source/i2c_control.vhd sub00/vhpl05
AR uc_interface behaviour d:/my_design/example-10-1/i2c/xst/i2c/../../source/uc_interface.vhd sub00/vhpl07
EN upcnt4 NULL d:/my_design/example-10-1/i2c/xst/i2c/../../source/upcnt4.vhd sub00/vhpl00
EN uc_interface NULL d:/my_design/example-10-1/i2c/xst/i2c/../../source/uc_interface.vhd sub00/vhpl06
AR shift8 definition d:/my_design/example-10-1/i2c/xst/i2c/../../source/shift.vhd sub00/vhpl03
AR upcnt4 definition d:/my_design/example-10-1/i2c/xst/i2c/../../source/upcnt4.vhd sub00/vhpl01