i2c.twr

Xilinx ISE 官方源代码盘第十章

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Release 6.2i Trace G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.

D:/Xilinx/bin/nt/trce.exe -intstyle ise -e 3 -l 3 -xml i2c i2c.ncd -o i2c.twr
i2c.pcf


Design file:              i2c.ncd
Physical constraint file: i2c.pcf
Device,speed:             xc2s200,-6 (PRODUCTION 1.27 2003-12-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
   option. All paths that are not constrained will be reported in the
   unconstrained paths section(s) of the report.


Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  |  Clock |
Source      | clk (edge) | clk (edge) |Internal Clock(s) |  Phase |
------------+------------+------------+------------------+--------+
addr_bus<0> |    5.241(R)|   -3.202(R)|clk_BUFGP         |   0.000|
addr_bus<10>|    5.006(R)|   -4.306(R)|clk_BUFGP         |   0.000|
addr_bus<11>|    2.375(R)|   -1.675(R)|clk_BUFGP         |   0.000|
addr_bus<12>|    3.732(R)|   -3.032(R)|clk_BUFGP         |   0.000|
addr_bus<13>|    1.942(R)|   -1.242(R)|clk_BUFGP         |   0.000|
addr_bus<14>|    1.842(R)|   -1.142(R)|clk_BUFGP         |   0.000|
addr_bus<15>|    1.868(R)|   -1.168(R)|clk_BUFGP         |   0.000|
addr_bus<16>|    3.706(R)|   -3.006(R)|clk_BUFGP         |   0.000|
addr_bus<17>|    4.133(R)|   -3.433(R)|clk_BUFGP         |   0.000|
addr_bus<18>|    4.257(R)|   -3.557(R)|clk_BUFGP         |   0.000|
addr_bus<19>|    4.379(R)|   -3.679(R)|clk_BUFGP         |   0.000|
addr_bus<1> |    2.383(R)|   -0.690(R)|clk_BUFGP         |   0.000|
addr_bus<20>|    2.561(R)|   -1.861(R)|clk_BUFGP         |   0.000|
addr_bus<21>|    3.768(R)|   -3.068(R)|clk_BUFGP         |   0.000|
addr_bus<22>|    3.721(R)|   -3.021(R)|clk_BUFGP         |   0.000|
addr_bus<23>|    3.700(R)|   -3.000(R)|clk_BUFGP         |   0.000|
addr_bus<2> |    2.410(R)|   -0.646(R)|clk_BUFGP         |   0.000|
addr_bus<3> |    5.342(R)|   -2.307(R)|clk_BUFGP         |   0.000|
addr_bus<4> |    5.210(R)|   -3.608(R)|clk_BUFGP         |   0.000|
addr_bus<5> |    4.220(R)|   -2.517(R)|clk_BUFGP         |   0.000|
addr_bus<6> |    4.905(R)|   -3.145(R)|clk_BUFGP         |   0.000|
addr_bus<7> |    5.494(R)|   -3.360(R)|clk_BUFGP         |   0.000|
addr_bus<8> |    2.763(R)|   -2.063(R)|clk_BUFGP         |   0.000|
addr_bus<9> |    2.404(R)|   -1.704(R)|clk_BUFGP         |   0.000|
as          |    4.724(R)|   -0.662(R)|clk_BUFGP         |   0.000|
data_bus<0> |    1.860(R)|   -1.160(R)|clk_BUFGP         |   0.000|
data_bus<1> |    1.784(R)|   -0.542(R)|clk_BUFGP         |   0.000|
data_bus<2> |    3.410(R)|   -1.371(R)|clk_BUFGP         |   0.000|
data_bus<3> |    1.809(R)|   -0.598(R)|clk_BUFGP         |   0.000|
data_bus<4> |    1.900(R)|   -0.909(R)|clk_BUFGP         |   0.000|
data_bus<5> |    2.449(R)|   -0.484(R)|clk_BUFGP         |   0.000|
data_bus<6> |    1.886(R)|   -1.073(R)|clk_BUFGP         |   0.000|
data_bus<7> |    1.666(R)|   -0.476(R)|clk_BUFGP         |   0.000|
ds          |    2.400(R)|    0.000(R)|clk_BUFGP         |   0.000|
r_w         |    5.013(R)|   -1.579(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
data_bus<0> |   12.227(R)|clk_BUFGP         |   0.000|
data_bus<1> |   11.670(R)|clk_BUFGP         |   0.000|
data_bus<2> |   12.269(R)|clk_BUFGP         |   0.000|
data_bus<3> |   11.381(R)|clk_BUFGP         |   0.000|
data_bus<4> |   11.975(R)|clk_BUFGP         |   0.000|
data_bus<5> |   11.381(R)|clk_BUFGP         |   0.000|
data_bus<6> |   12.229(R)|clk_BUFGP         |   0.000|
data_bus<7> |   11.581(R)|clk_BUFGP         |   0.000|
dtack       |   10.458(R)|clk_BUFGP         |   0.000|
irq         |   10.545(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock scl to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  |  Clock |
Destination | to PAD     |Internal Clock(s) |  Phase |
------------+------------+------------------+--------+
mcf         |   12.411(F)|N8941             |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    8.165|         |         |         |
scl            |    3.697|   12.352|         |         |
sda            |    9.643|    7.752|         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock scl
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |         |         |    7.249|         |
scl            |         |         |         |    7.518|
sda            |         |         |    0.832|    6.203|
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock sda
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
scl            |   -2.368|   -2.368|   -0.872|   -0.872|
---------------+---------+---------+---------+---------+

Pad to Pad
---------------+---------------+---------+
Source Pad     |Destination Pad|  Delay  |
---------------+---------------+---------+
r_w            |data_bus<0>    |   10.416|
r_w            |data_bus<1>    |    9.859|
r_w            |data_bus<2>    |   10.458|
r_w            |data_bus<3>    |    9.570|
r_w            |data_bus<4>    |   10.164|
r_w            |data_bus<5>    |    9.570|
r_w            |data_bus<6>    |   10.418|
r_w            |data_bus<7>    |    9.770|
---------------+---------------+---------+

Analysis completed Thu Jul 29 11:30:39 2004
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Peak Memory Usage: 50 MB