i2c_map.vhd

Xilinx ISE 官方源代码盘第十章

  signal uC_CTRL_rsta_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd1_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd4_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_5_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_7_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_7_FFX_RST : STD_LOGIC; 
  signal uC_CTRL_data_en_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd3_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd6_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_state_FFd2_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_i2c_header_en_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_state_FFd2_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_state_FFd5_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_maas_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd2_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_5_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_5_FFX_RST : STD_LOGIC; 
  signal uC_CTRL_data_out_2_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_data_out_3_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_men_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_7_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_7_FFX_RST : STD_LOGIC; 
  signal uC_CTRL_data_out_4_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_madr_4_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_madr_4_FFX_RST : STD_LOGIC; 
  signal uC_CTRL_madr_6_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_mbcr_wr_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_madr_6_FFX_RST : STD_LOGIC; 
  signal uC_CTRL_madr_7_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd2_FFX_RST : STD_LOGIC; 
  signal uC_CTRL_stat_en_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_stat_en_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_scl_out_reg_FFY_SET : STD_LOGIC; 
  signal uC_CTRL_mal_bit_reset_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_1_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_1_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_3_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd5_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_gen_start_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_sda_out_reg_d1_FFY_SET : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_3_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_5_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_mif_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_7_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_7_FFX_RST : STD_LOGIC; 
  signal uC_CTRL_msta_FFY_RST : STD_LOGIC; 
  signal as_IFF_SET : STD_LOGIC; 
  signal I2C_CTRL_bus_busy_d1_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_srw_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_3_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_rxak_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_mal_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_1_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_3_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_1_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_3_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_shift_reg_ld_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_5_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_as_int_d1_FFY_SET : STD_LOGIC; 
  signal uC_CTRL_address_match_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_slave_sda_FFY_SET : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd3_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_msta_d1_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_mif_bit_reset_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_state_FFd7_FFY_SET : STD_LOGIC; 
  signal ds_IFF_SET : STD_LOGIC; 
  signal I2C_CTRL_stop_scl_reg_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_bus_busy_FFY_RST : STD_LOGIC; 
  signal sda_IFF_SET : STD_LOGIC; 
  signal scl_IFF_RST : STD_LOGIC; 
  signal dtack_OFF_SET : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_0_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_1_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_1_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_0_FFY_RST : STD_LOGIC; 
  signal clk_BUFGP_BUFG_CE : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal I2C_CTRL_I2CHEADER_REG_data_int : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal uC_CTRL_madr : STD_LOGIC_VECTOR ( 7 downto 1 ); 
  signal I2C_CTRL_CLKCNT_q_int : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal uC_CTRL_mbdr_micro : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal uC_CTRL_data_out : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal I2C_CTRL_mbdr_i2c : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal I2C_CTRL_I2CDATA_REG_data_int : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal I2C_CTRL_I2CDATA_REG_n0001 : STD_LOGIC_VECTOR ( 7 downto 0 ); 
begin
  GLOBAL_LOGIC1_ONE : X_ONE
    port map (
      O => GLOBAL_LOGIC1
    );
  GLOBAL_LOGIC0_ZERO : X_ZERO
    port map (
      O => GLOBAL_LOGIC0
    );
  I2C_CTRL_BITCNT_q_int_1_FFX_RSTOR : X_OR2
    port map (
      I0 => I2C_CTRL_BITCNT_q_int_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => I2C_CTRL_BITCNT_q_int_1_FFX_RST
    );
  I2C_CTRL_BITCNT_q_int_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => I2C_CTRL_BITCNT_q_int_inst_sum_1,
      CE => I2C_CTRL_BITCNT_n0002,
      CLK => I2C_CTRL_BITCNT_q_int_1_CKMUXNOT,
      SET => GND,
      RST => I2C_CTRL_BITCNT_q_int_1_FFX_RST,
      O => I2C_CTRL_BITCNT_q_int(1)
    );
  I2C_CTRL_BITCNT_q_int_1_FFY_RSTOR : X_OR2
    port map (
      I0 => I2C_CTRL_BITCNT_q_int_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => I2C_CTRL_BITCNT_q_int_1_FFY_RST
    );
  I2C_CTRL_BITCNT_q_int_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => I2C_CTRL_BITCNT_q_int_inst_sum_2,
      CE => I2C_CTRL_BITCNT_n0002,
      CLK => I2C_CTRL_BITCNT_q_int_1_CKMUXNOT,
      SET => GND,
      RST => I2C_CTRL_BITCNT_q_int_1_FFY_RST,
      O => I2C_CTRL_BITCNT_q_int(2)
    );
  I2C_CTRL_BITCNT_q_int_1_LOGIC_ZERO_27 : X_ZERO
    port map (
      O => I2C_CTRL_BITCNT_q_int_1_LOGIC_ZERO
    );
  I2C_CTRL_BITCNT_q_int_inst_cy_2_28 : X_MUX2
    port map (
      IA => I2C_CTRL_BITCNT_q_int_1_LOGIC_ZERO,
      IB => I2C_CTRL_BITCNT_q_int_1_CYINIT,
      SEL => I2C_CTRL_BITCNT_q_int_inst_lut3_11_O,
      O => I2C_CTRL_BITCNT_q_int_inst_cy_2
    );
  I2C_CTRL_BITCNT_q_int_inst_sum_1_29 : X_XOR2
    port map (
      I0 => I2C_CTRL_BITCNT_q_int_1_CYINIT,
      I1 => I2C_CTRL_BITCNT_q_int_inst_lut3_11_O,
      O => I2C_CTRL_BITCNT_q_int_inst_sum_1
    );
  I2C_CTRL_BITCNT_q_int_inst_lut3_11 : X_LUT4
    generic map(
      INIT => X"0004"
    )
    port map (
      ADR0 => I2C_CTRL_state_FFd5,
      ADR1 => I2C_CTRL_BITCNT_q_int(1),
      ADR2 => I2C_CTRL_state_FFd7,
      ADR3 => N9021,
      O => I2C_CTRL_BITCNT_q_int_inst_lut3_11_O
    );
  I2C_CTRL_BITCNT_q_int_inst_lut3_21 : X_LUT4
    generic map(
      INIT => X"0004"
    )
    port map (
      ADR0 => I2C_CTRL_state_FFd5,
      ADR1 => I2C_CTRL_BITCNT_q_int(2),
      ADR2 => I2C_CTRL_state_FFd7,
      ADR3 => N9025,
      O => I2C_CTRL_BITCNT_q_int_inst_lut3_21_O
    );
  I2C_CTRL_BITCNT_q_int_1_COUTUSED : X_BUF
    port map (
      I => I2C_CTRL_BITCNT_q_int_1_CYMUXG,
      O => I2C_CTRL_BITCNT_q_int_inst_cy_3
    );
  I2C_CTRL_BITCNT_q_int_1_CKINV : X_INV
    port map (
      I => N8941,
      O => I2C_CTRL_BITCNT_q_int_1_CKMUXNOT
    );
  I2C_CTRL_BITCNT_q_int_inst_cy_3_30 : X_MUX2
    port map (
      IA => I2C_CTRL_BITCNT_q_int_1_LOGIC_ZERO,
      IB => I2C_CTRL_BITCNT_q_int_inst_cy_2,
      SEL => I2C_CTRL_BITCNT_q_int_inst_lut3_21_O,
      O => I2C_CTRL_BITCNT_q_int_1_CYMUXG
    );
  I2C_CTRL_BITCNT_q_int_inst_sum_2_31 : X_XOR2
    port map (
      I0 => I2C_CTRL_BITCNT_q_int_inst_cy_2,
      I1 => I2C_CTRL_BITCNT_q_int_inst_lut3_21_O,
      O => I2C_CTRL_BITCNT_q_int_inst_sum_2
    );
  I2C_CTRL_BITCNT_q_int_1_SRMUX : X_INV
    port map (
      I => uC_CTRL_men,
      O => I2C_CTRL_BITCNT_q_int_1_SRMUX_OUTPUTNOT
    );
  I2C_CTRL_BITCNT_q_int_1_CYINIT_32 : X_BUF
    port map (
      I => I2C_CTRL_BITCNT_q_int_inst_cy_1,
      O => I2C_CTRL_BITCNT_q_int_1_CYINIT
    );
  I2C_CTRL_Mcompar_n0097_inst_cy_6_LOGIC_ONE_33 : X_ONE
    port map (
      O => I2C_CTRL_Mcompar_n0097_inst_cy_6_LOGIC_ONE
    );
  I2C_CTRL_Mcompar_n0097_inst_cy_6_LOGIC_ZERO_34 : X_ZERO
    port map (
      O => I2C_CTRL_Mcompar_n0097_inst_cy_6_LOGIC_ZERO
    );
  I2C_CTRL_Mcompar_n0097_inst_cy_5_35 : X_MUX2
    port map (
      IA => I2C_CTRL_Mcompar_n0097_inst_cy_6_LOGIC_ZERO,
      IB => I2C_CTRL_Mcompar_n0097_inst_cy_6_LOGIC_ONE,
      SEL => I2C_CTRL_Mcompar_n0097_inst_lut4_0,
      O => I2C_CTRL_Mcompar_n0097_inst_cy_5
    );
  I2C_CTRL_Mcompar_n0097_inst_lut4_01 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => I2C_CTRL_I2CHEADER_REG_data_int(1),
      ADR1 => uC_CTRL_madr(1),
      ADR2 => I2C_CTRL_I2CHEADER_REG_data_int(2),
      ADR3 => uC_CTRL_madr(2),
      O => I2C_CTRL_Mcompar_n0097_inst_lut4_0
    );
  I2C_CTRL_Mcompar_n0097_inst_lut4_11 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => I2C_CTRL_I2CHEADER_REG_data_int(3),
      ADR1 => uC_CTRL_madr(3),
      ADR2 => I2C_CTRL_I2CHEADER_REG_data_int(4),
      ADR3 => uC_CTRL_madr(4),
      O => I2C_CTRL_Mcompar_n0097_inst_lut4_1
    );
  I2C_CTRL_Mcompar_n0097_inst_cy_6_COUTUSED : X_BUF
    port map (
      I => I2C_CTRL_Mcompar_n0097_inst_cy_6_CYMUXG,
      O => I2C_CTRL_Mcompar_n0097_inst_cy_6
    );
  I2C_CTRL_Mcompar_n0097_inst_cy_6_36 : X_MUX2
    port map (
      IA => I2C_CTRL_Mcompar_n0097_inst_cy_6_LOGIC_ZERO,
      IB => I2C_CTRL_Mcompar_n0097_inst_cy_5,
      SEL => I2C_CTRL_Mcompar_n0097_inst_lut4_1,
      O => I2C_CTRL_Mcompar_n0097_inst_cy_6_CYMUXG
    );
  I2C_CTRL_addr_match_LOGIC_ZERO_37 : X_ZERO
    port map (
      O => I2C_CTRL_addr_match_LOGIC_ZERO
    );
  I2C_CTRL_Mcompar_n0097_inst_cy_7_38 : X_MUX2
    port map (
      IA => I2C_CTRL_addr_match_LOGIC_ZERO,
      IB => I2C_CTRL_addr_match_CYINIT,
      SEL => I2C_CTRL_Mcompar_n0097_inst_lut4_2,
      O => I2C_CTRL_Mcompar_n0097_inst_cy_7
    );
  I2C_CTRL_Mcompar_n0097_inst_lut4_21 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => I2C_CTRL_I2CHEADER_REG_data_int(5),
      ADR1 => uC_CTRL_madr(5),
      ADR2 => I2C_CTRL_I2CHEADER_REG_data_int(6),
      ADR3 => uC_CTRL_madr(6),
      O => I2C_CTRL_Mcompar_n0097_inst_lut4_2
    );
  I2C_CTRL_Mcompar_n0097_inst_lut4_31 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => I2C_CTRL_I2CHEADER_REG_data_int(7),
      ADR1 => uC_CTRL_madr(7),
      ADR2 => VCC,
      ADR3 => VCC,
      O => I2C_CTRL_Mcompar_n0097_inst_lut4_3
    );
  I2C_CTRL_addr_match_COUTUSED : X_BUF
    port map (
      I => I2C_CTRL_addr_match_CYMUXG,
      O => I2C_CTRL_addr_match
    );
  I2C_CTRL_Mcompar_n0097_inst_cy_8 : X_MUX2
    port map (
      IA => I2C_CTRL_addr_match_LOGIC_ZERO,
      IB => I2C_CTRL_Mcompar_n0097_inst_cy_7,
      SEL => I2C_CTRL_Mcompar_n0097_inst_lut4_3,
      O => I2C_CTRL_addr_match_CYMUXG
    );
  I2C_CTRL_addr_match_CYINIT_39 : X_BUF
    port map (
      I => I2C_CTRL_Mcompar_n0097_inst_cy_6,
      O => I2C_CTRL_addr_match_CYINIT
    );
  I2C_CTRL_n01121 : X_LUT4
    generic map(
      INIT => X"0004"
    )
    port map (
      ADR0 => I2C_CTRL_CLKCNT_q_int(1),
      ADR1 => I2C_CTRL_CLKCNT_q_int(0),
      ADR2 => I2C_CTRL_CLKCNT_q_int(2),
      ADR3 => I2C_CTRL_CLKCNT_q_int(3),
      O => I2C_CTRL_n0112_FROM
    );
  I2C_CTRL_n006710 : X_LUT4
    generic map(
      INIT => X"00F8"
    )
    port map (
      ADR0 => I2C_CTRL_n0112,
      ADR1 => I2C_CTRL_master_sda,
      ADR2 => uC_CTRL_rsta,
      ADR3 => I2C_CTRL_arb_lost,
      O => I2C_CTRL_n0112_GROM
    );
  I2C_CTRL_n0112_XUSED : X_BUF
    port map (
      I => I2C_CTRL_n0112_FROM,
      O => I2C_CTRL_n0112
    );
  I2C_CTRL_n0112_YUSED : X_BUF
    port map (
      I => I2C_CTRL_n0112_GROM,
      O => CHOICE323
    );
  Ker56961 : X_LUT4
    generic map(
      INIT => X"FBFF"
    )
    port map (
      ADR0 => uC_CTRL_prs_state_FFd4,
      ADR1 => uC_CTRL_prs_state_FFd2,
      ADR2 => r_w_IBUF,
      ADR3 => uC_CTRL_addr_en,
      O => uC_CTRL_madr_1_FROM
    );
  uC_CTRL_n0029_1_1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => uC_CTRL_madr(1),
      ADR1 => N5698,
      ADR2 => N8925,
      ADR3 => N5956,
      O => uC_CTRL_n0029_1_1_O
    );
  uC_CTRL_madr_1_XUSED : X_BUF
    port map (
      I => uC_CTRL_madr_1_FROM,
      O => N5698
    );
  uC_CTRL_madr_1_SRMUX : X_INV
    port map (
      I => reset_IBUF,
      O => uC_CTRL_madr_1_SRMUX_OUTPUTNOT
    );
  I2C_CTRL_state_FFd3_In20_SW1 : X_LUT4
    generic map(
      INIT => X"0233"
    )
    port map (
      ADR0 => CHOICE458,
      ADR1 => I2C_CTRL_arb_lost,
      ADR2 => N9075,
      ADR3 => N9085,
      O => I2C_CTRL_state_FFd3_FROM
    );
  I2C_CTRL_state_FFd3_In62 : X_LUT4
    generic map(
      INIT => X"FDEC"
    )
    port map (
      ADR0 => I2C_CTRL_addr_match,
      ADR1 => CHOICE466,
      ADR2 => I2C_CTRL_state_FFd3_In20_SW1_O,
      ADR3 => N8982,
      O => I2C_CTRL_state_FFd3_In62_O
    );
  I2C_CTRL_state_FFd3_XUSED : X_BUF
    port map (
      I => I2C_CTRL_state_FFd3_FROM,
      O => I2C_CTRL_state_FFd3_In20_SW1_O
    );
  I2C_CTRL_state_FFd3_CKINV : X_INV
    port map (