i2c_map.vhd

Xilinx ISE 官方源代码盘第十章

  signal I2C_CTRL_scl_state_FFd4_FROM : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd4_In : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd1_FROM : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd1_In : STD_LOGIC; 
  signal uC_CTRL_madr_1_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_n0041_2_14_O_FROM : STD_LOGIC; 
  signal uC_CTRL_n0041_2_14_O_GROM : STD_LOGIC; 
  signal uC_CTRL_n0029_4_1_O : STD_LOGIC; 
  signal uC_CTRL_madr_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0029_3_1_O : STD_LOGIC; 
  signal uC_CTRL_n0029_6_1_O : STD_LOGIC; 
  signal uC_CTRL_madr_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0029_5_1_O : STD_LOGIC; 
  signal uC_CTRL_madr_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0029_7_1_O : STD_LOGIC; 
  signal uC_CTRL_mbcr_wr_FROM : STD_LOGIC; 
  signal uC_CTRL_mbcr_wr_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n00361_O : STD_LOGIC; 
  signal N5945_FROM : STD_LOGIC; 
  signal N5945_GROM : STD_LOGIC; 
  signal N7297_FROM : STD_LOGIC; 
  signal N7297_GROM : STD_LOGIC; 
  signal I2C_CTRL_state_FFd3_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_n0041_4_14_O_FROM : STD_LOGIC; 
  signal uC_CTRL_n0041_4_14_O_GROM : STD_LOGIC; 
  signal I2C_CTRL_mcf_FROM : STD_LOGIC; 
  signal I2C_CTRL_mcf_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_mcf_GROM : STD_LOGIC; 
  signal I2C_CTRL_mcf_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_txak_FROM : STD_LOGIC; 
  signal uC_CTRL_txak_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n00341_O : STD_LOGIC; 
  signal uC_CTRL_n0041_5_14_O_FROM : STD_LOGIC; 
  signal uC_CTRL_n0041_5_14_O_GROM : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd2_FROM : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd2_In26_O : STD_LOGIC; 
  signal uC_CTRL_n0041_6_14_O_FROM : STD_LOGIC; 
  signal uC_CTRL_n0041_6_14_O_GROM : STD_LOGIC; 
  signal N5973_FROM : STD_LOGIC; 
  signal N5973_GROM : STD_LOGIC; 
  signal CHOICE362_FROM : STD_LOGIC; 
  signal CHOICE362_GROM : STD_LOGIC; 
  signal uC_CTRL_n0041_7_14_O_FROM : STD_LOGIC; 
  signal uC_CTRL_n0041_7_14_O_GROM : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd6_FROM : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd6_In24_O : STD_LOGIC; 
  signal I2C_CTRL_state_FFd2_In : STD_LOGIC; 
  signal I2C_CTRL_state_FFd1_In : STD_LOGIC; 
  signal I2C_CTRL_state_FFd2_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_i2c_header_en_FROM : STD_LOGIC; 
  signal I2C_CTRL_i2c_header_en_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0106 : STD_LOGIC; 
  signal I2C_CTRL_state_FFd5_FROM : STD_LOGIC; 
  signal I2C_CTRL_state_FFd5_In : STD_LOGIC; 
  signal I2C_CTRL_state_FFd5_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_maas_FROM : STD_LOGIC; 
  signal I2C_CTRL_maas_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0082 : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd2_In : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd1_In : STD_LOGIC; 
  signal uC_CTRL_n0053 : STD_LOGIC; 
  signal uC_CTRL_stat_en_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0052 : STD_LOGIC; 
  signal I2C_CTRL_scl_out_reg_FROM : STD_LOGIC; 
  signal I2C_CTRL_scl_out_reg_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_scl_out : STD_LOGIC; 
  signal uC_CTRL_mal_bit_reset_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0037 : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_1_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_shift_reg_en_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_shift_reg_en_FROM : STD_LOGIC; 
  signal I2C_CTRL_shift_reg_en_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0104 : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_3_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_5_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_7_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_gen_stop_FROM : STD_LOGIC; 
  signal I2C_CTRL_gen_stop_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0102 : STD_LOGIC; 
  signal I2C_CTRL_msta_rst_FROM : STD_LOGIC; 
  signal I2C_CTRL_msta_rst_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0066 : STD_LOGIC; 
  signal I2C_CTRL_arb_lost_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_arb_lost_FROM : STD_LOGIC; 
  signal I2C_CTRL_arb_lost_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0117 : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd5_FROM : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd5_In : STD_LOGIC; 
  signal I2C_CTRL_gen_start_FROM : STD_LOGIC; 
  signal I2C_CTRL_gen_start_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0101 : STD_LOGIC; 
  signal I2C_CTRL_state_FFd6_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_state_FFd6_FROM : STD_LOGIC; 
  signal I2C_CTRL_state_FFd6_In : STD_LOGIC; 
  signal I2C_CTRL_state_FFd6_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_sda_out_reg_d1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal CHOICE258_FROM : STD_LOGIC; 
  signal CHOICE258_GROM : STD_LOGIC; 
  signal I2C_CTRL_n0088_FROM : STD_LOGIC; 
  signal I2C_CTRL_n0088_GROM : STD_LOGIC; 
  signal CHOICE173_FROM : STD_LOGIC; 
  signal CHOICE173_GROM : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_1_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_1_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_1_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_master_sda_FFY_SET : STD_LOGIC; 
  signal I2C_CTRL_master_sda_FROM : STD_LOGIC; 
  signal I2C_CTRL_master_sda_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0090 : STD_LOGIC; 
  signal CHOICE335_FROM : STD_LOGIC; 
  signal CHOICE335_GROM : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd4_FFY_SET : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd4_FROM : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd4_In : STD_LOGIC; 
  signal CHOICE229_FROM : STD_LOGIC; 
  signal CHOICE229_GROM : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_3_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_3_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_3_CKMUXNOT : STD_LOGIC; 
  signal uC_CTRL_madr_2_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_5_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_5_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_lut3_0_FROM : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_lut3_0_GROM : STD_LOGIC; 
  signal CHOICE109_FROM : STD_LOGIC; 
  signal CHOICE109_GROM : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_I2CHEADER_REG_data_int_7_CKMUXNOT : STD_LOGIC; 
  signal N6330_FROM : STD_LOGIC; 
  signal N6330_GROM : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_n0004_GROM : STD_LOGIC; 
  signal CHOICE236_FROM : STD_LOGIC; 
  signal CHOICE236_GROM : STD_LOGIC; 
  signal I2C_CTRL_bit_cnt_ld_FROM : STD_LOGIC; 
  signal I2C_CTRL_bit_cnt_ld_GROM : STD_LOGIC; 
  signal uC_CTRL_data_en_FROM : STD_LOGIC; 
  signal uC_CTRL_data_en_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0054 : STD_LOGIC; 
  signal CHOICE306_FROM : STD_LOGIC; 
  signal CHOICE306_GROM : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd3_FROM : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd3_In : STD_LOGIC; 
  signal I2C_CTRL_bus_busy_d1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_srw_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_sm_stop_FFY_RST : STD_LOGIC; 
  signal CHOICE222_FROM : STD_LOGIC; 
  signal CHOICE222_GROM : STD_LOGIC; 
  signal CHOICE102_GROM : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_lut3_3 : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_sum_3 : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_3_GROM : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_3_CYINIT : STD_LOGIC; 
  signal I2C_CTRL_n0073_FROM : STD_LOGIC; 
  signal I2C_CTRL_n0073_GROM : STD_LOGIC; 
  signal I2C_CTRL_rxak_CKMUXNOT : STD_LOGIC; 
  signal uC_CTRL_addr_en_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_addr_en_FROM : STD_LOGIC; 
  signal uC_CTRL_addr_en_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0051 : STD_LOGIC; 
  signal uC_CTRL_I23_N539_FROM : STD_LOGIC; 
  signal uC_CTRL_I23_N539_GROM : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd3_FROM : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd3_In : STD_LOGIC; 
  signal CHOICE123_GROM : STD_LOGIC; 
  signal N9025_FROM : STD_LOGIC; 
  signal N9025_GROM : STD_LOGIC; 
  signal I2C_CTRL_msta_d1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_sda_out_reg_FFY_SET : STD_LOGIC; 
  signal uC_CTRL_mif_bit_reset_FROM : STD_LOGIC; 
  signal uC_CTRL_mif_bit_reset_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0038 : STD_LOGIC; 
  signal CHOICE130_GROM : STD_LOGIC; 
  signal CHOICE435_FROM : STD_LOGIC; 
  signal CHOICE435_GROM : STD_LOGIC; 
  signal uC_CTRL_mien_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_state_FFd7_FROM : STD_LOGIC; 
  signal I2C_CTRL_state_FFd7_In : STD_LOGIC; 
  signal I2C_CTRL_state_FFd7_CKMUXNOT : STD_LOGIC; 
  signal N9060_FROM : STD_LOGIC; 
  signal N9060_GROM : STD_LOGIC; 
  signal CHOICE451_FROM : STD_LOGIC; 
  signal CHOICE451_GROM : STD_LOGIC; 
  signal CHOICE387_FROM : STD_LOGIC; 
  signal CHOICE387_GROM : STD_LOGIC; 
  signal N7361_FROM : STD_LOGIC; 
  signal N7361_GROM : STD_LOGIC; 
  signal uC_CTRL_as_int_d1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_address_match_FROM : STD_LOGIC; 
  signal uC_CTRL_address_match_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0045 : STD_LOGIC; 
  signal CHOICE146_FROM : STD_LOGIC; 
  signal CHOICE146_GROM : STD_LOGIC; 
  signal N6429_FROM : STD_LOGIC; 
  signal N6429_GROM : STD_LOGIC; 
  signal I2C_CTRL_slave_sda_FROM : STD_LOGIC; 
  signal I2C_CTRL_slave_sda_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0091 : STD_LOGIC; 
  signal uC_CTRL_mien_FFX_RST : STD_LOGIC; 
  signal CHOICE419_FROM : STD_LOGIC; 
  signal CHOICE419_GROM : STD_LOGIC; 
  signal N9064_GROM : STD_LOGIC; 
  signal I2C_CTRL_mal_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_mal_BYMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_n0172_FROM : STD_LOGIC; 
  signal I2C_CTRL_n0172_GROM : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_I24_N498_GROM : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_shift_reg_ld_FROM : STD_LOGIC; 
  signal I2C_CTRL_shift_reg_ld_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0105 : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_lut3_3 : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_sum_3 : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_3_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_3_GROM : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_3_CYINIT : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_mif_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_mif_BYMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_mbdr_i2c_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0171_GROM : STD_LOGIC; 
  signal CHOICE319_GROM : STD_LOGIC; 
  signal N6096_FROM : STD_LOGIC; 
  signal N6096_GROM : STD_LOGIC; 
  signal as_IDELAY : STD_LOGIC; 
  signal as_IBUF_0 : STD_LOGIC; 
  signal as_SRMUXNOT : STD_LOGIC; 
  signal uC_CTRL_msta_FROM : STD_LOGIC; 
  signal uC_CTRL_msta_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0032_O : STD_LOGIC; 
  signal ds_IDELAY : STD_LOGIC; 
  signal ds_IBUF : STD_LOGIC; 
  signal ds_SRMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_n0087_GROM : STD_LOGIC; 
  signal addr_bus_0_IBUF_1 : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_0_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_stop_scl_reg_FROM : STD_LOGIC; 
  signal I2C_CTRL_stop_scl_reg_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n0068 : STD_LOGIC; 
  signal addr_bus_1_IBUF_2 : STD_LOGIC; 
  signal addr_bus_2_IBUF_3 : STD_LOGIC; 
  signal uC_CTRL_I25_N498_GROM : STD_LOGIC; 
  signal addr_bus_3_IBUF_4 : STD_LOGIC; 
  signal CHOICE240_GROM : STD_LOGIC; 
  signal addr_bus_4_IBUF_5 : STD_LOGIC; 
  signal I2C_CTRL_bus_busy_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_bus_busy_BYMUXNOT : STD_LOGIC; 
  signal addr_bus_5_IBUF_6 : STD_LOGIC; 
  signal addr_bus_6_IBUF_7 : STD_LOGIC; 
  signal I2C_CTRL_scl_in_FFY_SET : STD_LOGIC; 
  signal I2C_CTRL_scl_in_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal addr_bus_7_IBUF_8 : STD_LOGIC; 
  signal mcf_ENABLE : STD_LOGIC; 
  signal mcf_TORGTS : STD_LOGIC; 
  signal mcf_OUTMUX : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_1_FFY_RST : STD_LOGIC; 
  signal addr_bus_8_IBUF_9 : STD_LOGIC; 
  signal I2C_CTRL_detect_stop_FFY_RST : STD_LOGIC; 
  signal addr_bus_9_IBUF_10 : STD_LOGIC; 
  signal I2C_CTRL_master_slave_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_master_slave_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_master_slave_CEMUXNOT : STD_LOGIC; 
  signal data_bus_0_ENABLE : STD_LOGIC; 
  signal data_bus_0_TORGTS : STD_LOGIC; 
  signal data_bus_0_OUTMUX : STD_LOGIC; 
  signal data_bus_0_IBUF : STD_LOGIC; 
  signal CHOICE346_FROM : STD_LOGIC; 
  signal CHOICE346_GROM : STD_LOGIC; 
  signal data_bus_1_ENABLE : STD_LOGIC; 
  signal data_bus_1_TORGTS : STD_LOGIC; 
  signal data_bus_1_OUTMUX : STD_LOGIC; 
  signal data_bus_1_IBUF : STD_LOGIC; 
  signal data_bus_2_ENABLE : STD_LOGIC; 
  signal data_bus_2_TORGTS : STD_LOGIC; 
  signal data_bus_2_OUTMUX : STD_LOGIC; 
  signal data_bus_2_IBUF : STD_LOGIC; 
  signal data_bus_3_ENABLE : STD_LOGIC; 
  signal data_bus_3_TORGTS : STD_LOGIC; 
  signal data_bus_3_OUTMUX : STD_LOGIC; 
  signal data_bus_3_IBUF : STD_LOGIC; 
  signal data_bus_4_ENABLE : STD_LOGIC; 
  signal data_bus_4_TORGTS : STD_LOGIC; 
  signal data_bus_4_OUTMUX : STD_LOGIC; 
  signal data_bus_4_IBUF : STD_LOGIC; 
  signal data_bus_5_ENABLE : STD_LOGIC; 
  signal data_bus_5_TORGTS : STD_LOGIC; 
  signal data_bus_5_OUTMUX : STD_LOGIC; 
  signal data_bus_5_IBUF : STD_LOGIC; 
  signal data_bus_6_ENABLE : STD_LOGIC; 
  signal data_bus_6_TORGTS : STD_LOGIC; 
  signal data_bus_6_OUTMUX : STD_LOGIC; 
  signal data_bus_6_IBUF : STD_LOGIC; 
  signal sda_ENABLE : STD_LOGIC; 
  signal sda_TORGTS : STD_LOGIC; 
  signal sda_OUTMUX : STD_LOGIC; 
  signal sda_LOGIC_ZERO : STD_LOGIC; 
  signal sda_IDELAY : STD_LOGIC; 
  signal sda_IBUF : STD_LOGIC; 
  signal sda_SRMUXNOT : STD_LOGIC; 
  signal data_bus_7_ENABLE : STD_LOGIC; 
  signal data_bus_7_TORGTS : STD_LOGIC; 
  signal data_bus_7_OUTMUX : STD_LOGIC; 
  signal data_bus_7_IBUF : STD_LOGIC; 
  signal irq_ENABLE : STD_LOGIC; 
  signal irq_TORGTS : STD_LOGIC; 
  signal irq_OUTMUX : STD_LOGIC; 
  signal irq_LOGIC_ZERO : STD_LOGIC; 
  signal r_w_IBUF_11 : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_3_FFY_RST : STD_LOGIC; 
  signal scl_ENABLE : STD_LOGIC; 
  signal scl_TORGTS : STD_LOGIC; 
  signal scl_OUTMUX : STD_LOGIC; 
  signal scl_LOGIC_ZERO : STD_LOGIC; 
  signal scl_ICLKNOT : STD_LOGIC; 
  signal scl_IDELAY : STD_LOGIC; 
  signal scl_IBUF : STD_LOGIC; 
  signal addr_bus_10_IBUF_12 : STD_LOGIC; 
  signal addr_bus_11_IBUF_13 : STD_LOGIC; 
  signal addr_bus_12_IBUF_14 : STD_LOGIC; 
  signal addr_bus_20_IBUF_15 : STD_LOGIC; 
  signal addr_bus_13_IBUF_16 : STD_LOGIC; 
  signal addr_bus_21_IBUF_17 : STD_LOGIC; 
  signal addr_bus_14_IBUF_18 : STD_LOGIC; 
  signal addr_bus_22_IBUF_19 : STD_LOGIC; 
  signal reset_IBUF_20 : STD_LOGIC; 
  signal addr_bus_15_IBUF_21 : STD_LOGIC; 
  signal addr_bus_23_IBUF_22 : STD_LOGIC; 
  signal addr_bus_16_IBUF_23 : STD_LOGIC; 
  signal addr_bus_17_IBUF_24 : STD_LOGIC; 
  signal addr_bus_18_IBUF_25 : STD_LOGIC; 
  signal addr_bus_19_IBUF_26 : STD_LOGIC; 
  signal dtack_ENABLE : STD_LOGIC; 
  signal dtack_TORGTS : STD_LOGIC; 
  signal dtack_OUTMUX : STD_LOGIC; 
  signal uC_CTRL_dtack_int : STD_LOGIC; 
  signal dtack_OD : STD_LOGIC; 
  signal dtack_SRMUXNOT : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_3_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_0_FROM : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_0_CYMUXG : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_0_GROM : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_cy_0 : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_0_LOGIC_ZERO : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_sum_0 : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_lut3_1 : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_sum_1 : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_1_CYMUXG : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_1_LOGIC_ZERO : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_lut3_21_O : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_cy_2 : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_1_CYINIT : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_sum_2 : STD_LOGIC; 
  signal I2C_CTRL_bit_cnt_ld_rt : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_0_CYMUXG : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_0_GROM : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_cy_0 : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_0_LOGIC_ZERO : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_sum_0 : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_0_CKMUXNOT : STD_LOGIC; 
  signal uC_CTRL_data_out_0_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_data_out_1_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_5_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_3_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_7_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_5_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_gen_stop_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_data_int_7_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_msta_rst_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_txak_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_mcf_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd2_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_data_out_5_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_data_out_6_FFY_RST : STD_LOGIC; 
  signal uC_CTRL_data_out_7_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd7_FFY_SET : STD_LOGIC;