i2c_map.vhd

Xilinx ISE 官方源代码盘第十章

-- Xilinx Vhdl netlist produced by netgen application (version G.28)
-- Command       : -intstyle ise -s 6 -pcf i2c.pcf -ngm i2c.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim i2c_map.ncd i2c_map.vhd 
-- Input file    : i2c_map.ncd
-- Output file   : i2c_map.vhd
-- Design name   : i2c
-- # of Entities : 1
-- Xilinx        : D:/Xilinx
-- Device        : 2s200pq208-6 (PRODUCTION 1.27 2003-12-13)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity i2c is
  port (
    dtack : out STD_LOGIC; 
    irq : out STD_LOGIC; 
    scl : inout STD_LOGIC; 
    sda : inout STD_LOGIC; 
    mcf : inout STD_LOGIC; 
    r_w : in STD_LOGIC := 'X'; 
    reset : in STD_LOGIC := 'X'; 
    ds : in STD_LOGIC := 'X'; 
    as : in STD_LOGIC := 'X'; 
    clk : in STD_LOGIC := 'X'; 
    data_bus : inout STD_LOGIC_VECTOR ( 7 downto 0 ); 
    addr_bus : in STD_LOGIC_VECTOR ( 23 downto 0 ) 
  );
end i2c;

architecture Structure of i2c is
  signal I2C_CTRL_BITCNT_n0002 : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_cy_1 : STD_LOGIC; 
  signal N8941 : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_cy_3 : STD_LOGIC; 
  signal I2C_CTRL_state_FFd5 : STD_LOGIC; 
  signal I2C_CTRL_state_FFd7 : STD_LOGIC; 
  signal N9021 : STD_LOGIC; 
  signal N9025 : STD_LOGIC; 
  signal uC_CTRL_men : STD_LOGIC; 
  signal I2C_CTRL_Mcompar_n0097_inst_cy_6 : STD_LOGIC; 
  signal I2C_CTRL_addr_match : STD_LOGIC; 
  signal I2C_CTRL_n0112 : STD_LOGIC; 
  signal I2C_CTRL_master_sda : STD_LOGIC; 
  signal uC_CTRL_rsta : STD_LOGIC; 
  signal I2C_CTRL_arb_lost : STD_LOGIC; 
  signal CHOICE323 : STD_LOGIC; 
  signal clk_BUFGP : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd4 : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd2 : STD_LOGIC; 
  signal r_w_IBUF : STD_LOGIC; 
  signal uC_CTRL_addr_en : STD_LOGIC; 
  signal N5698 : STD_LOGIC; 
  signal N8925 : STD_LOGIC; 
  signal N5956 : STD_LOGIC; 
  signal reset_IBUF : STD_LOGIC; 
  signal CHOICE458 : STD_LOGIC; 
  signal N9075 : STD_LOGIC; 
  signal N9085 : STD_LOGIC; 
  signal CHOICE466 : STD_LOGIC; 
  signal I2C_CTRL_state_FFd3_In20_SW1_O : STD_LOGIC; 
  signal N8982 : STD_LOGIC; 
  signal I2C_CTRL_n0052 : STD_LOGIC; 
  signal I2C_CTRL_state_FFd3 : STD_LOGIC; 
  signal CHOICE362 : STD_LOGIC; 
  signal uC_CTRL_mtx : STD_LOGIC; 
  signal I2C_CTRL_master_slave : STD_LOGIC; 
  signal CHOICE368 : STD_LOGIC; 
  signal I2C_CTRL_state_FFd4_In15_SW1_O : STD_LOGIC; 
  signal N8976 : STD_LOGIC; 
  signal I2C_CTRL_state_FFd4 : STD_LOGIC; 
  signal N8927 : STD_LOGIC; 
  signal CHOICE236 : STD_LOGIC; 
  signal I2C_CTRL_state_FFd1 : STD_LOGIC; 
  signal N8939 : STD_LOGIC; 
  signal CHOICE233 : STD_LOGIC; 
  signal I2C_CTRL_sm_stop : STD_LOGIC; 
  signal N5712 : STD_LOGIC; 
  signal CHOICE229 : STD_LOGIC; 
  signal I2C_CTRL_n008924_O : STD_LOGIC; 
  signal N5667 : STD_LOGIC; 
  signal uC_CTRL_mien : STD_LOGIC; 
  signal N8935 : STD_LOGIC; 
  signal N5945 : STD_LOGIC; 
  signal N8931 : STD_LOGIC; 
  signal I2C_CTRL_sda_out_reg : STD_LOGIC; 
  signal CHOICE333 : STD_LOGIC; 
  signal CHOICE335 : STD_LOGIC; 
  signal CHOICE332 : STD_LOGIC; 
  signal CHOICE330 : STD_LOGIC; 
  signal CHOICE319 : STD_LOGIC; 
  signal I2C_CTRL_n006761_O : STD_LOGIC; 
  signal uC_CTRL_data_en : STD_LOGIC; 
  signal N5687 : STD_LOGIC; 
  signal N8923 : STD_LOGIC; 
  signal N5934 : STD_LOGIC; 
  signal I2C_CTRL_sda_in : STD_LOGIC; 
  signal CHOICE452 : STD_LOGIC; 
  signal CHOICE451 : STD_LOGIC; 
  signal N8929 : STD_LOGIC; 
  signal N5676 : STD_LOGIC; 
  signal N8991 : STD_LOGIC; 
  signal N7361 : STD_LOGIC; 
  signal CHOICE306 : STD_LOGIC; 
  signal CHOICE311 : STD_LOGIC; 
  signal uC_CTRL_n0041_1_34_O : STD_LOGIC; 
  signal uC_CTRL_mal_bit_reset : STD_LOGIC; 
  signal CHOICE258 : STD_LOGIC; 
  signal CHOICE260 : STD_LOGIC; 
  signal I2C_CTRL_n017631_O : STD_LOGIC; 
  signal I2C_CTRL_n0176 : STD_LOGIC; 
  signal N8933 : STD_LOGIC; 
  signal N7297 : STD_LOGIC; 
  signal CHOICE371 : STD_LOGIC; 
  signal CHOICE382 : STD_LOGIC; 
  signal uC_CTRL_n0041_2_0_O : STD_LOGIC; 
  signal CHOICE296 : STD_LOGIC; 
  signal CHOICE299 : STD_LOGIC; 
  signal CHOICE291 : STD_LOGIC; 
  signal uC_CTRL_n0041_3_38_O : STD_LOGIC; 
  signal uC_CTRL_cntrl_en : STD_LOGIC; 
  signal N8937 : STD_LOGIC; 
  signal CHOICE387 : STD_LOGIC; 
  signal CHOICE398 : STD_LOGIC; 
  signal uC_CTRL_n0041_4_0_O : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd1 : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd6 : STD_LOGIC; 
  signal I2C_CTRL_clk_cnt_rst : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd2 : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd4 : STD_LOGIC; 
  signal N6220 : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_n0002 : STD_LOGIC; 
  signal CHOICE403 : STD_LOGIC; 
  signal CHOICE414 : STD_LOGIC; 
  signal uC_CTRL_n0041_5_0_O : STD_LOGIC; 
  signal CHOICE435 : STD_LOGIC; 
  signal CHOICE446 : STD_LOGIC; 
  signal uC_CTRL_n0041_6_0_O : STD_LOGIC; 
  signal CHOICE419 : STD_LOGIC; 
  signal CHOICE430 : STD_LOGIC; 
  signal uC_CTRL_n0041_7_0_O : STD_LOGIC; 
  signal CHOICE240 : STD_LOGIC; 
  signal CHOICE246 : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd7_In48_SW0_O : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd7 : STD_LOGIC; 
  signal uC_CTRL_n003520_O : STD_LOGIC; 
  signal N6030 : STD_LOGIC; 
  signal N9046 : STD_LOGIC; 
  signal CHOICE281 : STD_LOGIC; 
  signal I2C_CTRL_n0041 : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd5 : STD_LOGIC; 
  signal CHOICE182 : STD_LOGIC; 
  signal N9035 : STD_LOGIC; 
  signal I2C_CTRL_n0043 : STD_LOGIC; 
  signal uC_CTRL_stat_en : STD_LOGIC; 
  signal I2C_CTRL_srw : STD_LOGIC; 
  signal uC_CTRL_n0041_2_14_O : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd3 : STD_LOGIC; 
  signal uC_CTRL_mbcr_wr : STD_LOGIC; 
  signal uC_CTRL_dtack_com : STD_LOGIC; 
  signal I2C_CTRL_mal : STD_LOGIC; 
  signal uC_CTRL_n0041_4_14_O : STD_LOGIC; 
  signal I2C_CTRL_n0042 : STD_LOGIC; 
  signal I2C_CTRL_detect_start : STD_LOGIC; 
  signal I2C_CTRL_mcf : STD_LOGIC; 
  signal uC_CTRL_txak : STD_LOGIC; 
  signal uC_CTRL_msta : STD_LOGIC; 
  signal I2C_CTRL_bus_busy : STD_LOGIC; 
  signal uC_CTRL_n0041_5_14_O : STD_LOGIC; 
  signal I2C_CTRL_stop_scl_reg : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd2_In17_O : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd3 : STD_LOGIC; 
  signal I2C_CTRL_scl_in : STD_LOGIC; 
  signal I2C_CTRL_maas : STD_LOGIC; 
  signal uC_CTRL_n0041_6_14_O : STD_LOGIC; 
  signal N5973 : STD_LOGIC; 
  signal I2C_CTRL_n0170 : STD_LOGIC; 
  signal uC_CTRL_n0041_7_14_O : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd6_In2_O : STD_LOGIC; 
  signal CHOICE222 : STD_LOGIC; 
  signal I2C_CTRL_state_FFd2 : STD_LOGIC; 
  signal I2C_CTRL_state_FFd6 : STD_LOGIC; 
  signal I2C_CTRL_n0071 : STD_LOGIC; 
  signal I2C_CTRL_i2c_header_en : STD_LOGIC; 
  signal I2C_CTRL_n0175 : STD_LOGIC; 
  signal uC_CTRL_ds_int : STD_LOGIC; 
  signal uC_CTRL_address_match : STD_LOGIC; 
  signal uC_CTRL_prs_state_FFd1 : STD_LOGIC; 
  signal uC_CTRL_as_int_d1 : STD_LOGIC; 
  signal addr_bus_2_IBUF : STD_LOGIC; 
  signal addr_bus_1_IBUF : STD_LOGIC; 
  signal N6009 : STD_LOGIC; 
  signal I2C_CTRL_scl_out_reg : STD_LOGIC; 
  signal CHOICE72 : STD_LOGIC; 
  signal CHOICE76 : STD_LOGIC; 
  signal I2C_CTRL_I2CDATA_REG_n0004 : STD_LOGIC; 
  signal I2C_CTRL_shift_reg_ld : STD_LOGIC; 
  signal I2C_CTRL_shift_reg_en : STD_LOGIC; 
  signal I2C_CTRL_n0174 : STD_LOGIC; 
  signal I2C_CTRL_detect_stop : STD_LOGIC; 
  signal I2C_CTRL_msta_d1 : STD_LOGIC; 
  signal I2C_CTRL_gen_stop : STD_LOGIC; 
  signal I2C_CTRL_n0171 : STD_LOGIC; 
  signal I2C_CTRL_sda_out_reg_d1 : STD_LOGIC; 
  signal I2C_CTRL_msta_rst : STD_LOGIC; 
  signal I2C_CTRL_n0173 : STD_LOGIC; 
  signal I2C_CTRL_gen_start : STD_LOGIC; 
  signal N6395 : STD_LOGIC; 
  signal N5802 : STD_LOGIC; 
  signal I2C_CTRL_n0088 : STD_LOGIC; 
  signal CHOICE173 : STD_LOGIC; 
  signal N6242 : STD_LOGIC; 
  signal N9064 : STD_LOGIC; 
  signal CHOICE166 : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_lut3_0 : STD_LOGIC; 
  signal addr_bus_0_IBUF : STD_LOGIC; 
  signal addr_bus_7_IBUF : STD_LOGIC; 
  signal addr_bus_5_IBUF : STD_LOGIC; 
  signal addr_bus_6_IBUF : STD_LOGIC; 
  signal addr_bus_3_IBUF : STD_LOGIC; 
  signal addr_bus_4_IBUF : STD_LOGIC; 
  signal CHOICE109 : STD_LOGIC; 
  signal N7085 : STD_LOGIC; 
  signal uC_CTRL_mif_bit_reset : STD_LOGIC; 
  signal N6330 : STD_LOGIC; 
  signal I2C_CTRL_n0177 : STD_LOGIC; 
  signal I2C_CTRL_bus_busy_d1 : STD_LOGIC; 
  signal N6795 : STD_LOGIC; 
  signal I2C_CTRL_bit_cnt_ld : STD_LOGIC; 
  signal I2C_CTRL_mif : STD_LOGIC; 
  signal as_IBUF : STD_LOGIC; 
  signal N6296 : STD_LOGIC; 
  signal CHOICE102 : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_cy_3 : STD_LOGIC; 
  signal I2C_CTRL_n0073 : STD_LOGIC; 
  signal I2C_CTRL_n0087 : STD_LOGIC; 
  signal I2C_CTRL_rxak : STD_LOGIC; 
  signal CHOICE114 : STD_LOGIC; 
  signal uC_CTRL_I23_N539 : STD_LOGIC; 
  signal N6676 : STD_LOGIC; 
  signal addr_bus_11_IBUF : STD_LOGIC; 
  signal addr_bus_8_IBUF : STD_LOGIC; 
  signal addr_bus_9_IBUF : STD_LOGIC; 
  signal addr_bus_20_IBUF : STD_LOGIC; 
  signal CHOICE123 : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_lut3_01_O : STD_LOGIC; 
  signal addr_bus_21_IBUF : STD_LOGIC; 
  signal addr_bus_22_IBUF : STD_LOGIC; 
  signal addr_bus_23_IBUF : STD_LOGIC; 
  signal addr_bus_12_IBUF : STD_LOGIC; 
  signal CHOICE130 : STD_LOGIC; 
  signal CHOICE350 : STD_LOGIC; 
  signal N8972 : STD_LOGIC; 
  signal N8970 : STD_LOGIC; 
  signal N9060 : STD_LOGIC; 
  signal uC_CTRL_as_int : STD_LOGIC; 
  signal addr_bus_13_IBUF : STD_LOGIC; 
  signal addr_bus_14_IBUF : STD_LOGIC; 
  signal addr_bus_15_IBUF : STD_LOGIC; 
  signal N9068 : STD_LOGIC; 
  signal CHOICE148 : STD_LOGIC; 
  signal addr_bus_19_IBUF : STD_LOGIC; 
  signal addr_bus_10_IBUF : STD_LOGIC; 
  signal addr_bus_16_IBUF : STD_LOGIC; 
  signal CHOICE146 : STD_LOGIC; 
  signal addr_bus_17_IBUF : STD_LOGIC; 
  signal addr_bus_18_IBUF : STD_LOGIC; 
  signal N6429 : STD_LOGIC; 
  signal I2C_CTRL_slave_sda : STD_LOGIC; 
  signal I2C_CTRL_I35_N498 : STD_LOGIC; 
  signal I2C_CTRL_n0103 : STD_LOGIC; 
  signal I2C_CTRL_n0172 : STD_LOGIC; 
  signal uC_CTRL_I24_N498 : STD_LOGIC; 
  signal CHOICE176 : STD_LOGIC; 
  signal N9079 : STD_LOGIC; 
  signal N6096 : STD_LOGIC; 
  signal N9031 : STD_LOGIC; 
  signal clk_BUFGP_IBUFG : STD_LOGIC; 
  signal CHOICE214 : STD_LOGIC; 
  signal uC_CTRL_I25_N498 : STD_LOGIC; 
  signal CHOICE346 : STD_LOGIC; 
  signal I2C_CTRL_CLKCNT_q_int_inst_cy_1 : STD_LOGIC; 
  signal GLOBAL_LOGIC1 : STD_LOGIC; 
  signal GLOBAL_LOGIC0 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_1_FFX_RST : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_1_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_lut3_11_O : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_sum_1 : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_1_CYMUXG : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_1_LOGIC_ZERO : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_lut3_21_O : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_cy_2 : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_1_CYINIT : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_inst_sum_2 : STD_LOGIC; 
  signal I2C_CTRL_BITCNT_q_int_1_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_Mcompar_n0097_inst_lut4_0 : STD_LOGIC; 
  signal I2C_CTRL_Mcompar_n0097_inst_cy_6_CYMUXG : STD_LOGIC; 
  signal I2C_CTRL_Mcompar_n0097_inst_lut4_1 : STD_LOGIC; 
  signal I2C_CTRL_Mcompar_n0097_inst_cy_5 : STD_LOGIC; 
  signal I2C_CTRL_Mcompar_n0097_inst_cy_6_LOGIC_ZERO : STD_LOGIC; 
  signal I2C_CTRL_Mcompar_n0097_inst_cy_6_LOGIC_ONE : STD_LOGIC; 
  signal I2C_CTRL_Mcompar_n0097_inst_lut4_2 : STD_LOGIC; 
  signal I2C_CTRL_addr_match_CYMUXG : STD_LOGIC; 
  signal I2C_CTRL_Mcompar_n0097_inst_lut4_3 : STD_LOGIC; 
  signal I2C_CTRL_Mcompar_n0097_inst_cy_7 : STD_LOGIC; 
  signal I2C_CTRL_addr_match_LOGIC_ZERO : STD_LOGIC; 
  signal I2C_CTRL_addr_match_CYINIT : STD_LOGIC; 
  signal I2C_CTRL_n0112_FROM : STD_LOGIC; 
  signal I2C_CTRL_n0112_GROM : STD_LOGIC; 
  signal uC_CTRL_madr_1_FROM : STD_LOGIC; 
  signal uC_CTRL_madr_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0029_1_1_O : STD_LOGIC; 
  signal I2C_CTRL_state_FFd3_FROM : STD_LOGIC; 
  signal I2C_CTRL_state_FFd3_In62_O : STD_LOGIC; 
  signal I2C_CTRL_state_FFd3_CKMUXNOT : STD_LOGIC; 
  signal I2C_CTRL_state_FFd4_FFY_RST : STD_LOGIC; 
  signal I2C_CTRL_state_FFd4_FROM : STD_LOGIC; 
  signal I2C_CTRL_state_FFd4_In47_O : STD_LOGIC; 
  signal I2C_CTRL_state_FFd4_CKMUXNOT : STD_LOGIC; 
  signal uC_CTRL_madr_2_FROM : STD_LOGIC; 
  signal uC_CTRL_madr_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0029_2_1_O : STD_LOGIC; 
  signal I2C_CTRL_sm_stop_FROM : STD_LOGIC; 
  signal I2C_CTRL_n008930_O : STD_LOGIC; 
  signal I2C_CTRL_sm_stop_CKMUXNOT : STD_LOGIC; 
  signal uC_CTRL_n00311_O : STD_LOGIC; 
  signal uC_CTRL_mien_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n00331_O : STD_LOGIC; 
  signal I2C_CTRL_sda_out_reg_FROM : STD_LOGIC; 
  signal I2C_CTRL_sda_out_reg_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_n006768_O : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_0_FROM : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0039_0_1_O : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_1_FROM : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0039_1_1_O : STD_LOGIC; 
  signal CHOICE458_FROM : STD_LOGIC; 
  signal CHOICE458_GROM : STD_LOGIC; 
  signal uC_CTRL_n0039_3_1_O : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0039_2_1_O : STD_LOGIC; 
  signal uC_CTRL_data_out_0_FROM : STD_LOGIC; 
  signal uC_CTRL_data_out_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0041_0_O : STD_LOGIC; 
  signal uC_CTRL_data_out_1_FROM : STD_LOGIC; 
  signal uC_CTRL_data_out_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0041_1_55_O : STD_LOGIC; 
  signal I2C_CTRL_n017631_O_FROM : STD_LOGIC; 
  signal I2C_CTRL_n017631_O_GROM : STD_LOGIC; 
  signal uC_CTRL_n0039_5_1_O : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0039_4_1_O : STD_LOGIC; 
  signal uC_CTRL_data_out_2_FROM : STD_LOGIC; 
  signal uC_CTRL_data_out_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0041_2_73_O : STD_LOGIC; 
  signal uC_CTRL_data_out_3_FROM : STD_LOGIC; 
  signal uC_CTRL_data_out_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0041_3_47_O : STD_LOGIC; 
  signal uC_CTRL_men_FROM : STD_LOGIC; 
  signal uC_CTRL_men_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n00301_O : STD_LOGIC; 
  signal uC_CTRL_n0039_7_1_O : STD_LOGIC; 
  signal uC_CTRL_mbdr_micro_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0039_6_1_O : STD_LOGIC; 
  signal uC_CTRL_data_out_4_FROM : STD_LOGIC; 
  signal uC_CTRL_data_out_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0041_4_73_O : STD_LOGIC; 
  signal N6220_FROM : STD_LOGIC; 
  signal N6220_GROM : STD_LOGIC; 
  signal uC_CTRL_data_out_5_FROM : STD_LOGIC; 
  signal uC_CTRL_data_out_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0041_5_73_O : STD_LOGIC; 
  signal uC_CTRL_data_out_6_FROM : STD_LOGIC; 
  signal uC_CTRL_data_out_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0041_6_73_O : STD_LOGIC; 
  signal uC_CTRL_data_out_7_FROM : STD_LOGIC; 
  signal uC_CTRL_data_out_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n0041_7_73_O : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd7_FROM : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal I2C_CTRL_scl_state_FFd7_In48_O : STD_LOGIC; 
  signal uC_CTRL_rsta_FROM : STD_LOGIC; 
  signal uC_CTRL_rsta_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal uC_CTRL_n003529_O : STD_LOGIC;