i2c.syr

Xilinx ISE 官方源代码盘第十章

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <state> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <scl_state> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <prs_state> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# Counters                         : 2
 4-bit up counter                  : 2
# Registers                        : 71
 1-bit register                    : 65
 8-bit register                    : 6
# Comparators                      : 1
 7-bit comparator equal            : 1
# Multiplexers                     : 2
 8-bit 2-to-1 multiplexer          : 2
# Tristates                        : 5
 1-bit tristate buffer             : 4
 8-bit tristate buffer             : 1
# Xors                             : 1
 1-bit xor2                        : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1710 - FF/Latch  <madr_0> (without init value) is constant in block <uc_interface>.
WARNING:Xst:1291 - FF/Latch <mbdr_read> is unconnected in block <uC_CTRL>.
WARNING:Xst:1291 - FF/Latch <uC_CTRL_mbdr_read> is unconnected in block <i2c>.

Optimizing unit <i2c> ...
Loading device for application Xst from file 'v200.nph' in environment D:/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block i2c, actual ratio is 5.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : i2c.ngr
Top Level Output File Name         : i2c
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 42

Macro Statistics :
# Registers                        : 53
#      1-bit register              : 47
#      8-bit register              : 6
# Counters                         : 2
#      4-bit up counter            : 2
# Multiplexers                     : 2
#      2-to-1 multiplexer          : 2
# Tristates                        : 5
#      1-bit tristate buffer       : 4
#      8-bit tristate buffer       : 1
# Comparators                      : 1
#      7-bit comparator equal      : 1

Cell Usage :
# BELS                             : 259
#      GND                         : 1
#      LUT1                        : 7
#      LUT2                        : 36
#      LUT2_D                      : 3
#      LUT3                        : 51
#      LUT3_D                      : 5
#      LUT3_L                      : 3
#      LUT4                        : 63
#      LUT4_D                      : 10
#      LUT4_L                      : 59
#      MUXCY                       : 12
#      VCC                         : 1
#      XORCY                       : 8
# FlipFlops/Latches                : 119
#      FDC                         : 53
#      FDC_1                       : 9
#      FDCE                        : 34
#      FDCPE                       : 8
#      FDE_1                       : 1
#      FDP                         : 13
#      FDP_1                       : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 41
#      IBUF                        : 28
#      IOBUF                       : 10
#      OBUF                        : 1
#      OBUFT                       : 2
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200pq208-6 

 Number of Slices:                     129  out of   2352     5%  
 Number of Slice Flip Flops:           119  out of   4704     2%  
 Number of 4 input LUTs:               237  out of   4704     5%  
 Number of bonded IOBs:                 41  out of    144    28%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
N8941(scl_IOBUF:O)                 | NONE(*)(I2C_CTRL_I2CHEADER_REG_data_int_5)| 30    |
clk                                | BUFGP                  | 87    |
N8939(sda_IOBUF:O)                 | NONE(*)(I2C_CTRL_detect_start)| 2     |
-----------------------------------+------------------------+-------+
(*) These 2 clock signal(s) are generated by combinatorial logic,
and XST is not able to identify which are the primary clock signals.
Please use the CLOCK_SIGNAL constraint to specify the clock signal(s) generated by combinatorial logic.

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 9.738ns (Maximum Frequency: 102.690MHz)
   Minimum input arrival time before clock: 8.226ns
   Maximum output required time after clock: 11.670ns
   Maximum combinational path delay: 10.137ns

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'scl_IOBUF:O'
Delay:               9.738ns (Levels of Logic = 3)
  Source:            I2C_CTRL_state_FFd5 (FF)
  Destination:       I2C_CTRL_BITCNT_q_int_2 (FF)
  Source Clock:      scl_IOBUF:O falling
  Destination Clock: scl_IOBUF:O falling

  Data Path: I2C_CTRL_state_FFd5 to I2C_CTRL_BITCNT_q_int_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q           17   1.085   2.610  I2C_CTRL_state_FFd5 (I2C_CTRL_state_FFd5)
     LUT2:I0->O            1   0.549   1.035  I2C_CTRL__n0098_SW0 (N6795)
     LUT4_D:I3->O          1   0.549   1.035  I2C_CTRL__n0098 (I2C_CTRL_bit_cnt_ld)
     LUT4:I2->O            4   0.549   1.440  I2C_CTRL_BITCNT__n00021 (I2C_CTRL_BITCNT__n0002)
     FDCPE:CE                  0.886          I2C_CTRL_BITCNT_q_int_0
    ----------------------------------------
    Total                      9.738ns (3.618ns logic, 6.120ns route)
                                       (37.2% logic, 62.8% route)

-------------------------------------------------------------------------
Timing constraint: Default period analysis for Clock 'clk'
Delay:               9.585ns (Levels of Logic = 3)
  Source:            I2C_CTRL_scl_state_FFd7 (FF)
  Destination:       I2C_CTRL_CLKCNT_q_int_0 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: I2C_CTRL_scl_state_FFd7 to I2C_CTRL_CLKCNT_q_int_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDP:C->Q             12   1.085   2.160  I2C_CTRL_scl_state_FFd7 (I2C_CTRL_scl_state_FFd7)
     LUT3:I1->O            3   0.549   1.332  Ker60281 (N6030)
     LUT3_D:I2->O          1   0.549   1.035  I2C_CTRL_clk_cnt_rst_SW17 (I2C_CTRL_clk_cnt_rst)
     LUT4:I0->O            4   0.549   1.440  I2C_CTRL_CLKCNT__n0002 (I2C_CTRL_CLKCNT__n0002)
     FDCPE:CE                  0.886          I2C_CTRL_CLKCNT_q_int_0
    ----------------------------------------
    Total                      9.585ns (3.618ns logic, 5.967ns route)
                                       (37.7% logic, 62.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
Offset:              8.226ns (Levels of Logic = 5)
  Source:            as (PAD)
  Destination:       uC_CTRL_address_match (FF)
  Destination Clock: clk rising

  Data Path: as to uC_CTRL_address_match
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             4   0.776   1.440  as_IBUF (as_IBUF)
     LUT3:I1->O            1   0.549   1.035  uC_CTRL__n004562 (CHOICE146)
     LUT4:I1->O            1   0.549   1.035  uC_CTRL__n004570_SW0 (N9068)
     LUT4:I3->O            1   0.549   1.035  uC_CTRL__n004570 (CHOICE148)
     LUT4:I3->O            1   0.549   0.000  uC_CTRL__n0045101 (uC_CTRL__n0045)
     FDC:D                     0.709          uC_CTRL_address_match
    ----------------------------------------
    Total                      8.226ns (3.681ns logic, 4.545ns route)
                                       (44.7% logic, 55.3% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'scl_IOBUF:O'
Offset:              7.085ns (Levels of Logic = 1)
  Source:            I2C_CTRL_mcf (FF)
  Destination:       mcf (PAD)
  Source Clock:      scl_IOBUF:O falling

  Data Path: I2C_CTRL_mcf to mcf
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC_1:C->Q            3   1.085   1.332  I2C_CTRL_mcf (I2C_CTRL_mcf)
     OBUF:I->O                 4.668          mcf_OBUF (mcf)
    ----------------------------------------
    Total                      7.085ns (5.753ns logic, 1.332ns route)
                                       (81.2% logic, 18.8% route)

-------------------------------------------------------------------------
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
Offset:              11.670ns (Levels of Logic = 3)
  Source:            I2C_CTRL_arb_lost (FF)
  Destination:       sda (PAD)
  Source Clock:      clk rising

  Data Path: I2C_CTRL_arb_lost to sda
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q            17   1.085   2.610  I2C_CTRL_arb_lost (I2C_CTRL_arb_lost)
     LUT2:I0->O            1   0.549   1.035  I2C_CTRL_I35_EnableTr_INV_SW0 (N6429)
     LUT4:I2->O            1   0.549   1.035  I2C_CTRL_I35_EnableTr_INV (I2C_CTRL_I35_N498)
     IOBUF:T->IO               4.807          sda_IOBUF (sda)
    ----------------------------------------
    Total                     11.670ns (6.990ns logic, 4.680ns route)
                                       (59.9% logic, 40.1% route)

-------------------------------------------------------------------------
Timing constraint: Default path analysis
Delay:               10.137ns (Levels of Logic = 3)
  Source:            r_w (PAD)
  Destination:       data_bus<0> (PAD)

  Data Path: r_w to data_bus<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            12   0.776   2.160  r_w_IBUF (r_w_IBUF)
     LUT3:I0->O            8   0.549   1.845  uC_CTRL_I23_EnableTr_INV1 (uC_CTRL_I23_N539)
     IOBUF:T->IO               4.807          data_bus_6_IOBUF (data_bus<6>)
    ----------------------------------------
    Total                     10.137ns (6.132ns logic, 4.005ns route)
                                       (60.5% logic, 39.5% route)

=========================================================================
CPU : 6.20 / 7.03 s | Elapsed : 6.00 / 7.00 s
 
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Total memory usage is 65876 kilobytes