i2c.syr

Xilinx ISE 官方源代码盘第十章

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: i2c.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : i2c.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : i2c
Output Format                      : NGC
Target Device                      : xc2s200-6-pq208

---- Source Options
Top Module Name                    : i2c
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : i2c.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
Optimize Instantiated Primitives   : NO
tristate2logic                     : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file d:/my_design/example-10-1/i2c/xst/i2c/../../source/upcnt4.vhd in Library work.
Entity <upcnt4> (Architecture <DEFINITION>) compiled.
Compiling vhdl file d:/my_design/example-10-1/i2c/xst/i2c/../../source/shift.vhd in Library work.
Entity <SHIFT8> (Architecture <DEFINITION>) compiled.
Compiling vhdl file d:/my_design/example-10-1/i2c/xst/i2c/../../source/i2c_control.vhd in Library work.
Entity <i2c_control> (Architecture <behave>) compiled.
Compiling vhdl file d:/my_design/example-10-1/i2c/xst/i2c/../../source/uc_interface.vhd in Library work.
Entity <uC_interface> (Architecture <BEHAVIOUR>) compiled.
Compiling vhdl file d:/my_design/example-10-1/i2c/xst/i2c/../../source/i2c.vhd in Library work.
Entity <i2c> (Architecture <behave>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <i2c> (Architecture <behave>).
Entity <i2c> analyzed. Unit <i2c> generated.

Analyzing Entity <i2c_control> (Architecture <behave>).
Entity <i2c_control> analyzed. Unit <i2c_control> generated.

Analyzing Entity <UPCNT4> (Architecture <definition>).
Entity <UPCNT4> analyzed. Unit <UPCNT4> generated.

Analyzing Entity <SHIFT8> (Architecture <definition>).
Entity <SHIFT8> analyzed. Unit <SHIFT8> generated.

Analyzing generic Entity <uc_interface> (Architecture <behaviour>).
	UC_ADDRESS = <u>0000000000000000
Entity <uc_interface> analyzed. Unit <uc_interface> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <SHIFT8>.
    Related source file is d:/my_design/example-10-1/i2c/xst/i2c/../../source/shift.vhd.
    Found 8-bit register for signal <data_int>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <SHIFT8> synthesized.


Synthesizing Unit <UPCNT4>.
    Related source file is d:/my_design/example-10-1/i2c/xst/i2c/../../source/upcnt4.vhd.
WARNING:Xst:1778 - Inout <qout> is assigned but never used.
    Found 4-bit up counter for signal <q_int>.
    Summary:
	inferred   1 Counter(s).
Unit <UPCNT4> synthesized.


Synthesizing Unit <uc_interface>.
    Related source file is d:/my_design/example-10-1/i2c/xst/i2c/../../source/uc_interface.vhd.
WARNING:Xst:1778 - Inout <mbdr_micro> is assigned but never used.
WARNING:Xst:1780 - Signal <addr_ready> is never used or assigned.
    Found finite state machine <FSM_0> for signal <prs_state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 11                                             |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit tristate buffer for signal <irq>.
    Found 1-bit register for signal <msta>.
    Found 1-bit register for signal <mbdr_read>.
    Found 1-bit tristate buffer for signal <dtack>.
    Found 1-bit register for signal <men>.
    Found 8-bit register for signal <mbdr_micro>.
    Found 1-bit register for signal <mal_bit_reset>.
    Found 1-bit register for signal <rsta>.
    Found 8-bit register for signal <madr>.
    Found 1-bit register for signal <mif_bit_reset>.
    Found 1-bit register for signal <mien>.
    Found 8-bit tristate buffer for signal <data_bus>.
    Found 1-bit register for signal <mbcr_wr>.
    Found 1-bit register for signal <mtx>.
    Found 1-bit register for signal <txak>.
    Found 1-bit register for signal <addr_en>.
    Found 1-bit register for signal <address_match>.
    Found 1-bit register for signal <as_int>.
    Found 1-bit register for signal <as_int_d1>.
    Found 1-bit register for signal <cntrl_en>.
    Found 1-bit register for signal <data_en>.
    Found 8-bit register for signal <data_out>.
    Found 1-bit register for signal <ds_int>.
    Found 1-bit register for signal <dtack_int>.
    Found 1-bit register for signal <stat_en>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  43 D-type flip-flop(s).
	inferred  10 Tristate(s).
Unit <uc_interface> synthesized.


Synthesizing Unit <i2c_control>.
    Related source file is d:/my_design/example-10-1/i2c/xst/i2c/../../source/i2c_control.vhd.
WARNING:Xst:1778 - Inout <srw> is assigned but never used.
WARNING:Xst:647 - Input <madr<0>> is never used.
WARNING:Xst:1778 - Inout <mbdr_i2c> is assigned but never used.
WARNING:Xst:646 - Signal <zero_sig> is assigned but never used.
WARNING:Xst:646 - Signal <i2c_shiftout> is assigned but never used.
WARNING:Xst:1780 - Signal <bit_cnt_clr> is never used or assigned.
    Found finite state machine <FSM_1> for signal <scl_state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 20                                             |
    | Inputs             | 11                                             |
    | Outputs            | 9                                              |
    | Clock              | sys_clk (rising_edge)                          |
    | Reset              | reset (negative)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | scl_idle                                       |
    | Power Up State     | scl_idle                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_2> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 21                                             |
    | Inputs             | 9                                              |
    | Outputs            | 8                                              |
    | Clock              | scl (falling_edge)                             |
    | Reset              | $n0052 (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <mal>.
    Found 1-bit register for signal <mcf>.
    Found 1-bit register for signal <mif>.
    Found 1-bit register for signal <srw>.
    Found 1-bit register for signal <maas>.
    Found 8-bit register for signal <mbdr_i2c>.
    Found 1-bit register for signal <rxak>.
    Found 1-bit tristate buffer for signal <sda>.
    Found 1-bit tristate buffer for signal <scl>.
    Found 1-bit register for signal <msta_rst>.
    Found 7-bit comparator equal for signal <$n0097> created at line 690.
    Found 1-bit xor2 for signal <$n0149> created at line 225.
    Found 1-bit register for signal <arb_lost>.
    Found 1-bit register for signal <bus_busy>.
    Found 1-bit register for signal <bus_busy_d1>.
    Found 1-bit register for signal <detect_start>.
    Found 1-bit register for signal <detect_stop>.
    Found 1-bit register for signal <gen_start>.
    Found 1-bit register for signal <gen_stop>.
    Found 1-bit register for signal <i2c_header_en>.
    Found 1-bit register for signal <master_sda>.
    Found 1-bit register for signal <master_slave>.
    Found 1-bit register for signal <msta_d1>.
    Found 1-bit register for signal <scl_in>.
    Found 1-bit register for signal <scl_out_reg>.
    Found 1-bit register for signal <sda_in>.
    Found 1-bit register for signal <sda_out_reg>.
    Found 1-bit register for signal <sda_out_reg_d1>.
    Found 1-bit register for signal <shift_reg_en>.
    Found 1-bit register for signal <shift_reg_ld>.
    Found 1-bit register for signal <slave_sda>.
    Found 1-bit register for signal <sm_stop>.
    Found 1-bit register for signal <stop_scl_reg>.
    Summary:
	inferred   2 Finite State Machine(s).
	inferred  36 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Tristate(s).
Unit <i2c_control> synthesized.


Synthesizing Unit <i2c>.
    Related source file is d:/my_design/example-10-1/i2c/xst/i2c/../../source/i2c.vhd.
WARNING:Xst:646 - Signal <mbdr_read> is assigned but never used.
Unit <i2c> synthesized.