i2c_synplify.srr

Xilinx ISE 官方源代码盘第十章

$ Start of Compile
#Mon Jul 26 09:52:59 2004

Synplicity VHDL Compiler, version 7.1, Build 158R, built Apr 18 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved

VHDL syntax check successful!

Compiler output is up to date.  No re-compile necessary

Synthesizing work.i2c.behave
Synthesizing work.uc_interface.behaviour
@N:"D:\My_Design\I2C\source\uc_interface.vhd":111:16:111:17|Using sequential encoding for type state_type
@W:"D:\My_Design\I2C\source\uc_interface.vhd":267:35:267:43|Signal prs_state in the sensitivity list is not used in the process
Post processing for work.uc_interface.behaviour
@W:"D:\My_Design\I2C\source\uc_interface.vhd":331:2:331:3|Optimizing register bit madr(0) to a constant 0
Synthesizing work.i2c_control.behave
@N:"D:\My_Design\I2C\source\i2c_control.vhd":104:16:104:17|Using onehot encoding for type state_type (idle="1000000")
@N:"D:\My_Design\I2C\source\i2c_control.vhd":108:20:108:21|Using onehot encoding for type scl_state_type (scl_idle="1000000")
@N:"D:\My_Design\I2C\source\i2c_control.vhd":233:4:233:11|Removed redundant assignment
@N:"D:\My_Design\I2C\source\i2c_control.vhd":535:3:535:14|Removed redundant assignment
@N:"D:\My_Design\I2C\source\i2c_control.vhd":575:3:575:6|Removed redundant assignment
@N:"D:\My_Design\I2C\source\i2c_control.vhd":635:3:635:5|Removed redundant assignment
@N:"D:\My_Design\I2C\source\i2c_control.vhd":684:3:684:10|Removed redundant assignment
Synthesizing work.upcnt4.definition
Post processing for work.upcnt4.definition
Synthesizing work.shift8.definition
Post processing for work.shift8.definition
Post processing for work.i2c_control.behave
Post processing for work.i2c.behave
@END
Process took 0.063 seconds realtime, 0.062 seconds cputime
Synplicity Xilinx Technology Mapper, version 7.1, Build 152R, built Apr  9 2002
Copyright (C) 1994-2002, Synplicity Inc.  All Rights Reserved
Automatic dissolve at startup in view:work.i2c_control(behave) of BITCNT(upcnt4)
Automatic dissolve at startup in view:work.i2c_control(behave) of I2CHEADER_REG(SHIFT8_I2CHEADER_REG)
Automatic dissolve at startup in view:work.i2c_control(behave) of I2CDATA_REG(SHIFT8)
Automatic dissolve at startup in view:work.i2c_control(behave) of CLKCNT(upcnt4)

Clock Buffers:
  Inserting Clock buffer for port clk,	TNM=clk
  Inserting Clock buffer on net scl_in, 	TNM=scl_in

Net buffering Report for view:work.i2c(behave):
No nets needed buffering.

@N|The option to pack flops in the IOB has not been specified 
Writing Analyst data base D:\My_Design\I2C\synplify\I2C_synplify\i2c_synplify.srm
Writing EDIF Netlist and constraint files
Writing VHDL Simulation files
Found clock clk with period 1000.00ns 
@W:"d:\my_design\i2c\source\i2c.vhd":33:2:33:4|Net scl_in_c appears to be a clock source which was not identified. Assuming default frequency. 
@W:"d:\my_design\i2c\source\i2c.vhd":32:2:32:4|Net sda_in_0 appears to be a clock source which was not identified. Assuming default frequency. 


##### START TIMING REPORT #####
# Timing Report written on Mon Jul 26 09:53:03 2004
#


Top view:              i2c
Slew propagation mode: worst
Paths requested:       5
Constraint File(s):    
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.
@N| Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock.



Performance Summary 
*******************


Worst slack in design: 990.202

                   Requested     Estimated     Requested     Estimated                 Clock   
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type    
-----------------------------------------------------------------------------------------------
clk                1.0 MHz       102.1 MHz     1000.000      9.798         990.202     inferred
System             1.0 MHz       111.6 MHz     1000.000      8.957         991.043     system  
===============================================================================================



Clock Relationships
*******************

Clocks            |    rise  to  rise     |    fall  to  fall   |    rise  to  fall   |    fall  to  rise 
----------------------------------------------------------------------------------------------------------
Starting  Ending  |  constraint  slack    |  constraint  slack  |  constraint  slack  |  constraint  slack
----------------------------------------------------------------------------------------------------------
clk       clk     |  1000.000    990.202  |  No paths    -      |  No paths    -      |  No paths    -    
==========================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port             Starting            User           Arrival     Required             
Name             Reference           Constraint     Time        Time         Slack   
                 Clock                                                               
-------------------------------------------------------------------------------------
addr_bus[0]      clk (rising)        NA             0.000       994.027      994.027 
addr_bus[1]      clk (rising)        NA             0.000       995.943      995.943 
addr_bus[2]      clk (rising)        NA             0.000       995.943      995.943 
addr_bus[3]      clk (rising)        NA             0.000       995.568      995.568 
addr_bus[4]      clk (rising)        NA             0.000       995.568      995.568 
addr_bus[5]      clk (rising)        NA             0.000       994.027      994.027 
addr_bus[6]      clk (rising)        NA             0.000       994.027      994.027 
addr_bus[7]      clk (rising)        NA             0.000       994.027      994.027 
addr_bus[8]      clk (rising)        NA             0.000       995.943      995.943 
addr_bus[9]      clk (rising)        NA             0.000       995.943      995.943 
addr_bus[10]     clk (rising)        NA             0.000       995.943      995.943 
addr_bus[11]     clk (rising)        NA             0.000       995.943      995.943 
addr_bus[12]     clk (rising)        NA             0.000       995.943      995.943 
addr_bus[13]     clk (rising)        NA             0.000       995.943      995.943 
addr_bus[14]     clk (rising)        NA             0.000       994.638      994.638 
addr_bus[15]     clk (rising)        NA             0.000       994.638      994.638 
addr_bus[16]     clk (rising)        NA             0.000       995.943      995.943 
addr_bus[17]     clk (rising)        NA             0.000       995.943      995.943 
addr_bus[18]     clk (rising)        NA             0.000       994.638      994.638 
addr_bus[19]     clk (rising)        NA             0.000       994.638      994.638 
addr_bus[20]     clk (rising)        NA             0.000       994.638      994.638 
addr_bus[21]     clk (rising)        NA             0.000       994.638      994.638 
addr_bus[22]     clk (rising)        NA             0.000       995.943      995.943 
addr_bus[23]     clk (rising)        NA             0.000       995.943      995.943 
as               clk (rising)        NA             0.000       997.460      997.460 
clk              NA                  NA             NA          NA           NA      
data_bus[0]      clk (rising)        NA             0.000       1000.000     1000.000
data_bus[1]      clk (rising)        NA             0.000       997.919      997.919 
data_bus[2]      clk (rising)        NA             0.000       997.248      997.248 
data_bus[3]      clk (rising)        NA             0.000       997.919      997.919 
data_bus[4]      clk (rising)        NA             0.000       997.248      997.248 
data_bus[5]      clk (rising)        NA             0.000       997.248      997.248 
data_bus[6]      clk (rising)        NA             0.000       997.919      997.919 
data_bus[7]      clk (rising)        NA             0.000       997.919      997.919 
ds               clk (rising)        NA             0.000       1000.000     1000.000
r_w              clk (rising)        NA             0.000       992.674      992.674 
reset            NA                  NA             NA          NA           NA      
scl              System (rising)     NA             0.000       993.903      993.903 
sda              System (rising)     NA             0.000       994.403      994.403 
=====================================================================================


Output Ports: 

Port            Starting             User           Arrival     Required             
Name            Reference            Constraint     Time        Time         Slack   
                Clock                                                                
-------------------------------------------------------------------------------------
data_bus[0]     clk (rising)         NA             8.316       1000.000     991.684 
data_bus[1]     clk (rising)         NA             8.316       1000.000     991.684 
data_bus[2]     clk (rising)         NA             8.316       1000.000     991.684 
data_bus[3]     clk (rising)         NA             8.316       1000.000     991.684 
data_bus[4]     clk (rising)         NA             8.316       1000.000     991.684 
data_bus[5]     clk (rising)         NA             8.316       1000.000     991.684 
data_bus[6]     clk (rising)         NA             8.316       1000.000     991.684 
data_bus[7]     clk (rising)         NA             8.316       1000.000     991.684 
dtack           clk (rising)         NA             0.000       1000.000     1000.000
irq             clk (rising)         NA             7.723       1000.000     992.277 
mcf             System (falling)     NA             6.480       1000.000     993.520 
scl             clk (rising)         NA             0.000       1000.000     1000.000
sda             clk (rising)         NA             9.798       1000.000     990.202 
=====================================================================================



====================================
Detailed Report for Clock: clk
====================================



Starting Points with worst slack 
********************************

                                                            Arrival            
Instance                  Type     Pin     Net              Time        Slack  
                                                                               
-------------------------------------------------------------------------------
I2C_CTRL.arb_lost         FDCE     Q       arb_lost         2.919       990.202
I2C_CTRL.sda_out_reg      FDPE     Q       sda_out_reg      2.149       990.972
I2C_CTRL.master_slave     FDCE     Q       master_slave     3.180       991.246
uC_CTRL.madr_1[1]         FDCE     Q       madr[1]          2.149       991.255