uc_interface.tlg

Xilinx ISE 官方源代码盘第十章

Synthesizing work.uc_interface.behaviour
@N:"D:\My_Design\I2C\source\uc_interface.vhd":111:16:111:17|Using sequential encoding for type state_type
@W:"D:\My_Design\I2C\source\uc_interface.vhd":267:35:267:43|Signal prs_state in the sensitivity list is not used in the process
Post processing for work.uc_interface.behaviour
@W:"D:\My_Design\I2C\source\uc_interface.vhd":331:2:331:3|Optimizing register bit madr(0) to a constant 0
@N:"D:\My_Design\I2C\source\uc_interface.vhd":183:2:183:3|Trying to extract state machine for register prs_state
Extracted state machine for register prs_state
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11