uc_interface.edf

Xilinx ISE 官方源代码盘第十章

(edif (rename uc_interface "uC_interface")
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2004 7 19 18 36 4)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "7.1, Build 152R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell IOBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port IO (direction INOUT))
           (port I (direction INPUT))
           (port T (direction INPUT))
         )
       )
    )
    (cell OBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell OBUFT (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
           (port T (direction INPUT))
         )
       )
    )
    (cell LUT4 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT3 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT2 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell BUFGP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell FDP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port PRE (direction INPUT))
         )
       )
    )
    (cell FDC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
         )
       )
    )
    (cell FDCE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell GND (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port G (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell uC_interface_cell_prs_state_0_3__hc (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename prs_state "prs_state[1:0]") 2) (direction OUTPUT))
           (port (rename prs_state_i_0 "prs_state_i[0]") (direction OUTPUT))
           (port (rename prs_state_rep0_i_1 "prs_state_rep0_i[1]") (direction OUTPUT))
           (port un5_as_1 (direction INPUT))
           (port address_match (direction INPUT))
           (port as_int_d1 (direction INPUT))
           (port ds_int (direction INPUT))
           (port reset_c_i (direction INPUT))
           (port clk_c (direction INPUT))
         )
         (contents
          (instance (rename prs_state_0 "prs_state[0]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename prs_state_1 "prs_state[1]") (viewRef PRIM (cellRef FDC (libraryRef UNILIB)))
          )
          (instance (rename prs_state_rep0_i_1 "prs_state_rep0_i[1]") (viewRef PRIM (cellRef FDP (libraryRef UNILIB)))
           (property IOB (string "TRUE"))
          )
          (instance (rename prs_state_i_0 "prs_state_i[0]") (viewRef PRIM (cellRef INV (libraryRef UNILIB)))          )
          (instance (rename prs_state_ns_i_1 "prs_state_ns_i[1]") (viewRef PRIM (cellRef INV (libraryRef UNILIB)))          )
          (instance prs_state_ns_8_0_or2 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property init (string "2AAA"))
          )
          (instance prs_state_ns_12_0 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property init (string "AAEA"))
          )
          (instance prs_state_ns_8_0 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property init (string "EEFE"))
          )
          (instance prs_state_ns_8_0_and2_0 (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property init (string "0800"))
          )
          (net (rename prs_state_iZ0Z_0 "prs_state_i[0]") (joined
           (portRef O (instanceRef prs_state_i_0))
           (portRef prs_state_i_0)
          ))
          (net (rename prs_state_rep0_iZ0Z_1 "prs_state_rep0_i[1]") (joined
           (portRef Q (instanceRef prs_state_rep0_i_1))
           (portRef prs_state_rep0_i_1)
          ))
          (net (rename prs_stateZ0Z_0 "prs_state[0]") (joined
           (portRef Q (instanceRef prs_state_0))
           (portRef I3 (instanceRef prs_state_ns_8_0_and2_0))
           (portRef I3 (instanceRef prs_state_ns_8_0))
           (portRef I1 (instanceRef prs_state_ns_12_0))
           (portRef I1 (instanceRef prs_state_ns_8_0_or2))
           (portRef I (instanceRef prs_state_i_0))
           (portRef (member prs_state 1))
          ))
          (net (rename prs_stateZ0Z_1 "prs_state[1]") (joined
           (portRef Q (instanceRef prs_state_1))
           (portRef I2 (instanceRef prs_state_ns_8_0_and2_0))
           (portRef I0 (instanceRef prs_state_ns_8_0_or2))
           (portRef (member prs_state 0))
          ))
          (net un5_as_1 (joined
           (portRef un5_as_1)
           (portRef I2 (instanceRef prs_state_ns_8_0))
          ))
          (net address_match (joined
           (portRef address_match)
           (portRef I0 (instanceRef prs_state_ns_8_0_and2_0))
           (portRef I2 (instanceRef prs_state_ns_12_0))
          ))
          (net as_int_d1 (joined
           (portRef as_int_d1)
           (portRef I3 (instanceRef prs_state_ns_8_0_or2))
          ))
          (net ds_int (joined
           (portRef ds_int)
           (portRef I1 (instanceRef prs_state_ns_8_0_and2_0))
           (portRef I3 (instanceRef prs_state_ns_12_0))
           (portRef I2 (instanceRef prs_state_ns_8_0_or2))
          ))
          (net reset_c_i (joined
           (portRef reset_c_i)
           (portRef PRE (instanceRef prs_state_rep0_i_1))
           (portRef CLR (instanceRef prs_state_1))
           (portRef CLR (instanceRef prs_state_0))
          ))
          (net clk_c (joined
           (portRef clk_c)
           (portRef C (instanceRef prs_state_rep0_i_1))
           (portRef C (instanceRef prs_state_1))
           (portRef C (instanceRef prs_state_0))
          ))
          (net (rename prs_state_ns_0 "prs_state_ns[0]") (joined
           (portRef O (instanceRef prs_state_ns_8_0))
           (portRef D (instanceRef prs_state_0))
          ))
          (net (rename prs_state_ns_1 "prs_state_ns[1]") (joined
           (portRef O (instanceRef prs_state_ns_12_0))
           (portRef I (instanceRef prs_state_ns_i_1))
           (portRef D (instanceRef prs_state_1))
          ))
          (net (rename prs_state_ns_iZ0Z_1 "prs_state_ns_i[1]") (joined
           (portRef O (instanceRef prs_state_ns_i_1))
           (portRef D (instanceRef prs_state_rep0_i_1))
          ))
          (net (rename prs_state_ns_8_0_orZ0Z2 "prs_state_ns_8_0_or2") (joined
           (portRef O (instanceRef prs_state_ns_8_0_or2))
           (portRef I1 (instanceRef prs_state_ns_8_0))
           (portRef I0 (instanceRef prs_state_ns_12_0))
          ))
          (net N_289 (joined
           (portRef O (instanceRef prs_state_ns_8_0_and2_0))
           (portRef I0 (instanceRef prs_state_ns_8_0))
          ))
         )
       )
    )
    (cell (rename uc_interface "uC_interface") (cellType GENERIC)
       (view behaviour (viewType NETLIST)
         (interface
           (port (array (rename addr_bus "addr_bus(23:0)") 24) (direction INPUT))
           (port (array (rename data_bus "data_bus(7:0)") 8) (direction INOUT))
           (port (array (rename madr "madr(7:0)") 8) (direction OUTPUT))
           (port (array (rename mbdr_micro "mbdr_micro(7:0)") 8) (direction OUTPUT))
           (port (array (rename mbdr_i2c "mbdr_i2c(7:0)") 8) (direction INPUT))
           (port clk (direction INPUT)
 )
           (port reset (direction INPUT)
 )
           (port as (direction INPUT)
 )
           (port ds (direction INPUT)
 )
           (port r_w (direction INPUT)
 )
           (port dtack (direction OUTPUT))
           (port irq (direction OUTPUT))
           (port men (direction OUTPUT))
           (port mien (direction OUTPUT))
           (port msta (direction OUTPUT))
           (port mtx (direction OUTPUT))
           (port txak (direction OUTPUT))
           (port rsta (direction OUTPUT))
           (port mbcr_wr (direction OUTPUT))
           (port rsta_rst (direction INPUT)
 )
           (port mcf (direction INPUT)