i2c_synplify.edf

Xilinx ISE 官方源代码盘第十章

(edif (rename i2c_synplify "i2c")
  (edifVersion 2 0 0)
  (edifLevel 0)
  (keywordMap (keywordLevel 0))
  (status
    (written
      (timeStamp 2004 7 26 9 53 2)
      (author "Synplicity, Inc.")
      (program "Synplify Pro" (version "7.1, Build 152R"))
     )
   )
  (library VIRTEX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell IBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell IOBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port IO (direction INOUT))
           (port I (direction INPUT))
           (port T (direction INPUT))
         )
       )
    )
    (cell OBUF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
         )
       )
    )
    (cell OBUFT (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port O (direction OUTPUT))
           (port I (direction INPUT))
           (port T (direction INPUT))
         )
       )
    )
    (cell LUT4 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port I3 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT3 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port I2 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell LUT2 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I0 (direction INPUT))
           (port I1 (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell BUFGP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell BUFG (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
  )
  (library UNILIB
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell FDP_1 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port PRE (direction INPUT))
         )
       )
    )
    (cell FDP (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port PRE (direction INPUT))
         )
       )
    )
    (cell FDC_1 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
         )
       )
    )
    (cell FDC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
         )
       )
    )
    (cell FDE_1 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CE (direction INPUT))
         )
       )
    )
    (cell FDPE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port PRE (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell FDCE_1 (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell FDCE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port Q (direction OUTPUT))
           (port D (direction INPUT))
           (port C (direction INPUT)
 )
           (port CLR (direction INPUT))
           (port CE (direction INPUT))
         )
       )
    )
    (cell INV (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port I (direction INPUT))
           (port O (direction OUTPUT))
         )
       )
    )
    (cell GND (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port G (direction OUTPUT))
         )
       )
    )
    (cell VCC (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port P (direction OUTPUT))
         )
       )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell upcnt4_1 (cellType GENERIC)
       (view netlist (viewType NETLIST)
         (interface
           (port (array (rename bit_cnt "bit_cnt(3:0)") 4) (direction OUTPUT))
           (port state_0 (direction INPUT))
           (port state_2 (direction INPUT))
           (port state_4 (direction INPUT))
           (port N_279 (direction INPUT))
           (port detect_start (direction INPUT))
           (port men_i (direction INPUT))
           (port scl_in (direction INPUT))
         )
         (contents
          (instance (rename q_int_1 "q_int[1]") (viewRef PRIM (cellRef FDC_1 (libraryRef UNILIB)))
          )
          (instance (rename q_int_2 "q_int[2]") (viewRef PRIM (cellRef FDC_1 (libraryRef UNILIB)))
          )
          (instance (rename q_int_3 "q_int[3]") (viewRef PRIM (cellRef FDC_1 (libraryRef UNILIB)))
          )
          (instance (rename q_int_0 "q_int[0]") (viewRef PRIM (cellRef FDC_1 (libraryRef UNILIB)))
          )
          (instance (rename q_int_4_i_or2_0 "q_int_4_i_or2[0]") (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property init (string "AAAB"))
          )
          (instance N_237_i (viewRef PRIM (cellRef LUT2 (libraryRef VIRTEX)))
           (property init (string "1"))
          )
          (instance N_243_i (viewRef PRIM (cellRef LUT4 (libraryRef VIRTEX)))
           (property init (string "4414"))
          )
          (instance N_241_i (viewRef PRIM (cellRef LUT3 (libraryRef VIRTEX)))
           (property init (string "41"))
          )
          (instance N_239_i (viewRef PRIM (cellRef LUT3 (libraryRef VIRTEX)))
           (property init (string "14"))
          )
          (net state_0 (joined
           (portRef state_0)
           (portRef I3 (instanceRef q_int_4_i_or2_0))
          ))
          (net state_2 (joined
           (portRef state_2)
           (portRef I2 (instanceRef q_int_4_i_or2_0))
          ))
          (net state_4 (joined
           (portRef state_4)
           (portRef I1 (instanceRef q_int_4_i_or2_0))
          ))
          (net (rename bit_cnt_0 "bit_cnt(0)") (joined
           (portRef Q (instanceRef q_int_0))
           (portRef I2 (instanceRef N_239_i))
           (portRef I0 (instanceRef N_237_i))
           (portRef (member bit_cnt 3))
          ))
          (net (rename bit_cnt_1 "bit_cnt(1)") (joined
           (portRef Q (instanceRef q_int_1))
           (portRef I1 (instanceRef N_239_i))
           (portRef (member bit_cnt 2))
          ))
          (net (rename bit_cnt_2 "bit_cnt(2)") (joined
           (portRef Q (instanceRef q_int_2))
           (portRef I1 (instanceRef N_241_i))
           (portRef I2 (instanceRef N_243_i))
           (portRef (member bit_cnt 1))
          ))
          (net (rename bit_cnt_3 "bit_cnt(3)") (joined
           (portRef Q (instanceRef q_int_3))
           (portRef I1 (instanceRef N_243_i))
           (portRef (member bit_cnt 0))
          ))
          (net (rename n_279 "N_279") (joined
           (portRef N_279)
           (portRef I2 (instanceRef N_241_i))
           (portRef I3 (instanceRef N_243_i))
          ))
          (net detect_start (joined
           (portRef detect_start)
           (portRef I0 (instanceRef q_int_4_i_or2_0))
          ))
          (net men_i (joined
           (portRef men_i)
           (portRef CLR (instanceRef q_int_0))
           (portRef CLR (instanceRef q_int_3))
           (portRef CLR (instanceRef q_int_2))
           (portRef CLR (instanceRef q_int_1))
          ))