i2c_synplify.vhd

Xilinx ISE 官方源代码盘第十章

architecture beh of BUFG is
begin
  O <= I;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FDP_1 is
port(
  Q :  out std_logic;
  D :  in std_logic;
  C :  in std_logic;
  PRE :  in std_logic);
end FDP_1;

architecture beh of FDP_1 is
  signal CN : std_logic ;
begin
  CN <= not C;
  II_Q: prim_dff port map (Q, D, CN, '0', PRE);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FDP is
port(
  Q :  out std_logic;
  D :  in std_logic;
  C :  in std_logic;
  PRE :  in std_logic);
end FDP;

architecture beh of FDP is
begin
  II_Q: prim_dff port map (Q, D, C, '0', PRE);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FDC_1 is
port(
  Q :  out std_logic;
  D :  in std_logic;
  C :  in std_logic;
  CLR :  in std_logic);
end FDC_1;

architecture beh of FDC_1 is
  signal CN : std_logic ;
begin
  CN <= not C;
  II_Q: prim_dff port map (Q, D, CN, CLR, '0');
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FDC is
port(
  Q :  out std_logic;
  D :  in std_logic;
  C :  in std_logic;
  CLR :  in std_logic);
end FDC;

architecture beh of FDC is
begin
  II_Q: prim_dff port map (Q, D, C, CLR, '0');
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FDE_1 is
port(
  Q :  out std_logic;
  D :  in std_logic;
  C :  in std_logic;
  CE :  in std_logic);
end FDE_1;

architecture beh of FDE_1 is
  signal CN : std_logic ;
  signal FB : std_logic ;
  signal QZ : std_logic ;
begin
  CN <= not C;
  FB <= QZ after 100 ps when CE = '0' else D after 100 ps;
  II_Q: prim_dff port map (QZ, FB, CN, '0', '0');
  Q <= QZ;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FDPE is
port(
  Q :  out std_logic;
  D :  in std_logic;
  C :  in std_logic;
  PRE :  in std_logic;
  CE :  in std_logic);
end FDPE;

architecture beh of FDPE is
  signal FB : std_logic ;
  signal QZ : std_logic ;
begin
  FB <= QZ after 100 ps when CE = '0' else D after 100 ps;
  II_Q: prim_dff port map (QZ, FB, C, '0', PRE);
  Q <= QZ;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FDCE_1 is
port(
  Q :  out std_logic;
  D :  in std_logic;
  C :  in std_logic;
  CLR :  in std_logic;
  CE :  in std_logic);
end FDCE_1;

architecture beh of FDCE_1 is
  signal CN : std_logic ;
  signal FB : std_logic ;
  signal QZ : std_logic ;
begin
  CN <= not C;
  FB <= QZ after 100 ps when CE = '0' else D after 100 ps;
  II_Q: prim_dff port map (QZ, FB, CN, CLR, '0');
  Q <= QZ;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity FDCE is
port(
  Q :  out std_logic;
  D :  in std_logic;
  C :  in std_logic;
  CLR :  in std_logic;
  CE :  in std_logic);
end FDCE;

architecture beh of FDCE is
  signal FB : std_logic ;
  signal QZ : std_logic ;
begin
  FB <= QZ after 100 ps when CE = '0' else D after 100 ps;
  II_Q: prim_dff port map (QZ, FB, C, CLR, '0');
  Q <= QZ;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity INV is
port(
  I :  in std_logic;
  O :  out std_logic);
end INV;

architecture beh of INV is
begin
  O <= not I;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity GND is
port(
  G :  out std_logic);
end GND;

architecture beh of GND is
begin
  G <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity VCC is
port(
  P :  out std_logic);
end VCC;

architecture beh of VCC is
begin
  P <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity upcnt4_1 is
port(
  state_0 :  in std_logic;
  state_2 :  in std_logic;
  state_4 :  in std_logic;
  bit_cnt : out std_logic_vector(3 downto 0);
  N_279 :  in std_logic;
  detect_start :  in std_logic;
  men_i :  in std_logic;
  scl_in :  in std_logic);
end upcnt4_1;

architecture beh of upcnt4_1 is
  signal BIT_CNTZ : std_logic_vector(3 downto 0);
  signal N_239_I : std_logic ;
  signal N_241_I : std_logic ;
  signal N_243_I : std_logic ;
  signal N_237_I : std_logic ;
  signal N_281 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component FDC_1
    port(
      Q :  out std_logic;
      D :  in std_logic;
      C :  in std_logic;
      CLR :  in std_logic  );
  end component;
  component LUT4_AAAB
    port(
      I0 :  in std_logic;
      I1 :  in std_logic;
      I2 :  in std_logic;
      I3 :  in std_logic;
      O :  out std_logic  );
  end component;
  component LUT2_1
    port(
      I0 :  in std_logic;
      I1 :  in std_logic;
      O :  out std_logic  );
  end component;
  component LUT4_4414
    port(
      I0 :  in std_logic;
      I1 :  in std_logic;
      I2 :  in std_logic;
      I3 :  in std_logic;
      O :  out std_logic  );
  end component;
  component LUT3_41
    port(
      I0 :  in std_logic;
      I1 :  in std_logic;
      I2 :  in std_logic;
      O :  out std_logic  );
  end component;
  component LUT3_14
    port(
      I0 :  in std_logic;
      I1 :  in std_logic;
      I2 :  in std_logic;
      O :  out std_logic  );
  end component;
begin
  \II_Q_INT[1]\: FDC_1 port map (
      Q => BIT_CNTZ(1),
      D => N_239_I,
      C => scl_in,
      CLR => men_i);
  \II_Q_INT[2]\: FDC_1 port map (
      Q => BIT_CNTZ(2),
      D => N_241_I,
      C => scl_in,
      CLR => men_i);
  \II_Q_INT[3]\: FDC_1 port map (
      Q => BIT_CNTZ(3),
      D => N_243_I,
      C => scl_in,
      CLR => men_i);
  \II_Q_INT[0]\: FDC_1 port map (
      Q => BIT_CNTZ(0),
      D => N_237_I,
      C => scl_in,
      CLR => men_i);
  \II_Q_INT_4_I_OR2[0]\: LUT4_AAAB port map (
      I0 => detect_start,
      I1 => state_4,
      I2 => state_2,
      I3 => state_0,
      O => N_281);
  II_N_237_I: LUT2_1 port map (
      I0 => BIT_CNTZ(0),
      I1 => N_281,
      O => N_237_I);
  II_N_243_I: LUT4_4414 port map (
      I0 => N_281,
      I1 => BIT_CNTZ(3),
      I2 => BIT_CNTZ(2),
      I3 => N_279,
      O => N_243_I);
  II_N_241_I: LUT3_41 port map (
      I0 => N_281,
      I1 => BIT_CNTZ(2),
      I2 => N_279,
      O => N_241_I);
  II_N_239_I: LUT3_14 port map (
      I0 => N_281,
      I1 => BIT_CNTZ(1),
      I2 => BIT_CNTZ(0),
      O => N_239_I);
  GND <= '0';
  VCC <= '1';
  bit_cnt(0) <= BIT_CNTZ(0);
  bit_cnt(1) <= BIT_CNTZ(1);
  bit_cnt(2) <= BIT_CNTZ(2);
  bit_cnt(3) <= BIT_CNTZ(3);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity SHIFT8_1 is
port(
  i2c_header : out std_logic_vector(6 downto 0);
  i2c_shiftout :  out std_logic;
  i2c_header_en :  in std_logic;
  men_i :  in std_logic;
  scl_in :  in std_logic;
  sda_in :  in std_logic);
end SHIFT8_1;

architecture beh of SHIFT8_1 is
  signal I2C_HEADERZ : std_logic_vector(6 downto 0);
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component FDCE_1
    port(
      Q :  out std_logic;
      D :  in std_logic;
      C :  in std_logic;
      CLR :  in std_logic;
      CE :  in std_logic  );
  end component;
begin
  \II_DATA_OUT[0]\: FDCE_1 port map (
      Q => I2C_HEADERZ(0),
      D => sda_in,
      C => scl_in,
      CLR => men_i,
      CE => i2c_header_en);
  \II_DATA_OUT[1]\: FDCE_1 port map (
      Q => I2C_HEADERZ(1),
      D => I2C_HEADERZ(0),
      C => scl_in,
      CLR => men_i,
      CE => i2c_header_en);
  \II_DATA_OUT[2]\: FDCE_1 port map (
      Q => I2C_HEADERZ(2),
      D => I2C_HEADERZ(1),
      C => scl_in,
      CLR => men_i,
      CE => i2c_header_en);
  \II_DATA_OUT[3]\: FDCE_1 port map (
      Q => I2C_HEADERZ(3),
      D => I2C_HEADERZ(2),
      C => scl_in,
      CLR => men_i,
      CE => i2c_header_en);
  \II_DATA_OUT[4]\: FDCE_1 port map (
      Q => I2C_HEADERZ(4),
      D => I2C_HEADERZ(3),
      C => scl_in,
      CLR => men_i,
      CE => i2c_header_en);
  \II_DATA_OUT[5]\: FDCE_1 port map (
      Q => I2C_HEADERZ(5),
      D => I2C_HEADERZ(4),
      C => scl_in,
      CLR => men_i,
      CE => i2c_header_en);
  \II_DATA_OUT[6]\: FDCE_1 port map (
      Q => I2C_HEADERZ(6),
      D => I2C_HEADERZ(5),
      C => scl_in,
      CLR => men_i,
      CE => i2c_header_en);
  \II_DATA_OUT[7]\: FDCE_1 port map (
      Q => i2c_shiftout,
      D => I2C_HEADERZ(6),
      C => scl_in,
      CLR => men_i,
      CE => i2c_header_en);
  GND <= '0';
  VCC <= '1';
  i2c_header(0) <= I2C_HEADERZ(0);
  i2c_header(1) <= I2C_HEADERZ(1);
  i2c_header(2) <= I2C_HEADERZ(2);
  i2c_header(3) <= I2C_HEADERZ(3);
  i2c_header(4) <= I2C_HEADERZ(4);
  i2c_header(5) <= I2C_HEADERZ(5);
  i2c_header(6) <= I2C_HEADERZ(6);
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity SHIFT8 is
port(
  shift_reg : out std_logic_vector(6 downto 0);
  shift_reg_ld :  in std_logic;
  shift_reg_en :  in std_logic;
  G_236 :  in std_logic;
  G_235 :  in std_logic;
  G_242 :  in std_logic;
  shift_out :  out std_logic;
  G_241 :  in std_logic;
  G_240 :  in std_logic;
  G_239 :  in std_logic;
  G_238 :  in std_logic;
  men_i :  in std_logic;
  scl_in :  in std_logic;
  G_237 :  in std_logic);
end SHIFT8;

architecture beh of SHIFT8 is
  signal N_327_I : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component FDCE_1
    port(
      Q :  out std_logic;
      D :  in std_logic;
      C :  in std_logic;
      CLR :  in std_logic;
      CE :  in std_logic  );
  end component;
  component LUT2_E
    port(
      I0 :  in std_logic;
      I1 :  in std_logic;
      O :  out std_logic  );
  end component;
begin
  \II_DATA_OUT[2]\: FDCE_1 port map (
      Q => shift_reg(2),
      D => G_237,
      C => scl_in,
      CLR => men_i,
      CE => N_327_I);
  \II_DATA_OUT[3]\: FDCE_1 port map (
      Q => shift_reg(3),
      D => G_238,
      C => scl_in,
      CLR => men_i,
      CE => N_327_I);
  \II_DATA_OUT[4]\: FDCE_1 port map (
      Q => shift_reg(4),
      D => G_239,
      C => scl_in,
      CLR => men_i,
      CE => N_327_I);
  \II_DATA_OUT[5]\: FDCE_1 port map (
      Q => shift_reg(5),
      D => G_240,
      C => scl_in,
      CLR => men_i,
      CE => N_327_I);
  \II_DATA_OUT[6]\: FDCE_1 port map (
      Q => shift_reg(6),
      D => G_241,
      C => scl_in,
      CLR => men_i,
      CE => N_327_I);
  \II_DATA_OUT[7]\: FDCE_1 port map (
      Q => shift_out,
      D => G_242,
      C => scl_in,
      CLR => men_i,
      CE => N_327_I);
  \II_DATA_OUT[0]\: FDCE_1 port map (
      Q => shift_reg(0),
      D => G_235,
      C => scl_in,
      CLR => men_i,
      CE => N_327_I);
  \II_DATA_OUT[1]\: FDCE_1 port map (
      Q => shift_reg(1),
      D => G_236,
      C => scl_in,
      CLR => men_i,
      CE => N_327_I);
  II_N_327_I: LUT2_E port map (
      I0 => shift_reg_en,
      I1 => shift_reg_ld,
      O => N_327_I);
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity upcnt4 is
port(
  clk_cnt : out std_logic_vector(3 downto 0);
  clk_cnt_en :  in std_logic;
  un1_q_int_c2 :  in std_logic;
  clk_cnt_rst :  in std_logic;
  men_i :  in std_logic;
  clk_c :  in std_logic);
end upcnt4;

architecture beh of upcnt4 is
  signal Q_INT_4 : std_logic_vector(3 downto 0);
  signal CLK_CNTZ : std_logic_vector(3 downto 0);
  signal GND : std_logic ;
  signal VCC : std_logic ;
  component FDC
    port(
      Q :  out std_logic;
      D :  in std_logic;
      C :  in std_logic;
      CLR :  in std_logic  );
  end component;
  component LUT4_1444
    port(
      I0 :  in std_logic;
      I1 :  in std_logic;
      I2 :  in std_logic;
      I3 :  in std_logic;
      O :  out std_logic  );
  end component;
  component LUT3_14
    port(
      I0 :  in std_logic;
      I1 :  in std_logic;
      I2 :  in std_logic;
      O :  out std_logic  );
  end component;
begin
  \II_Q_INT[0]\: FDC port map (
      Q => CLK_CNTZ(0),
      D => Q_INT_4(0),
      C => clk_c,
      CLR => men_i);
  \II_Q_INT[1]\: FDC port map (
      Q => CLK_CNTZ(1),
      D => Q_INT_4(1),
      C => clk_c,
      CLR => men_i);
  \II_Q_INT[2]\: FDC port map (
      Q => CLK_CNTZ(2),
      D => Q_INT_4(2),
      C => clk_c,
      CLR => men_i);
  \II_Q_INT[3]\: FDC port map (
      Q => CLK_CNTZ(3),
      D => Q_INT_4(3),
      C => clk_c,
      CLR => men_i);
  \II_Q_INT_4[3]\: LUT4_1444 port map (
      I0 => clk_cnt_rst,
      I1 => CLK_CNTZ(3),
      I2 => un1_q_int_c2,
      I3 => CLK_CNTZ(2),
      O => Q_INT_4(3));
  \II_Q_INT