i2c_synplify.vhd

Xilinx ISE 官方源代码盘第十章

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_AAEA is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_AAEA;

architecture beh of LUT4_AAEA is
  signal N_6 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= N_6 or I0 after 100 ps;
  I3_I_0 <= not I3;
  N_6 <= I3_I_0 and I2 and I1 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_FEEE is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_FEEE;

architecture beh of LUT4_FEEE is
  signal N_6 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_6 <= I3 and I2 after 100 ps;
  O <= N_6 or I1 or I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_F8FA is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_F8FA;

architecture beh of LUT4_F8FA is
  signal N_6 : std_logic ;
  signal N_7 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_7 <= I3_I_0 or I1 after 100 ps;
  N_6 <= N_7 and I0 after 100 ps;
  O <= N_6 or I2 after 100 ps;
  I3_I_0 <= not I3;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_2000 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_2000;

architecture beh of LUT4_2000 is
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I1_I_0 <= not I1;
  O <= I3 and I2 and I1_I_0 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_1510 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_1510;

architecture beh of LUT4_1510 is
  signal N_6 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_6 <= I3 after 100 ps when I2 = '0' else I1_I_0 after 100 ps;
  O <= N_6 and I0_I_0 after 100 ps;
  I0_I_0 <= not I0;
  I1_I_0 <= not I1;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_FFF8 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_FFF8;

architecture beh of LUT4_FFF8 is
  signal N_6 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_6 <= I1 and I0 after 100 ps;
  O <= N_6 or I3 or I2 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT2_1 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  O :  out std_logic);
end LUT2_1;

architecture beh of LUT2_1 is
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I1_I_0 and I0_I_0 after 100 ps;
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_4051 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_4051;

architecture beh of LUT4_4051 is
  signal N_6 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_6 <= I3_I_0 after 100 ps when I1 = '0' else I2 after 100 ps;
  O <= N_6 and I0_I_0 after 100 ps;
  I0_I_0 <= not I0;
  I3_I_0 <= not I3;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_5551 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_5551;

architecture beh of LUT4_5551 is
  signal N_7 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= N_7 and I0_I_0 after 100 ps;
  I0_I_0 <= not I0;
  I1_I_0 <= not I1;
  N_7 <= I3 or I2 or I1_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_FFD8 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_FFD8;

architecture beh of LUT4_FFD8 is
  signal N_4 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_4 <= I2 after 100 ps when I0 = '0' else I1 after 100 ps;
  O <= N_4 or I3 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_EC is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_EC;

architecture beh of LUT3_EC is
  signal N_4 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_4 <= I2 and I0 after 100 ps;
  O <= N_4 or I1 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT2_D is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  O :  out std_logic);
end LUT2_D;

architecture beh of LUT2_D is
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I1 or I0_I_0 after 100 ps;
  I0_I_0 <= not I0;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0111 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0111;

architecture beh of LUT4_0111 is
  signal N_10 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_10 <= I3_I_0 or I2_I_0 after 100 ps;
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  I3_I_0 <= not I3;
  I2_I_0 <= not I2;
  O <= N_10 and I1_I_0 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_FE is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_FE;

architecture beh of LUT3_FE is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I2 or I1 or I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT2_E is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  O :  out std_logic);
end LUT2_E;

architecture beh of LUT2_E is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I1 or I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_AAA8 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_AAA8;

architecture beh of LUT4_AAA8 is
  signal N_5 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= N_5 and I0 after 100 ps;
  N_5 <= I3 or I2 or I1 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_5515 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_5515;

architecture beh of LUT4_5515 is
  signal N_8 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= N_8 and I0_I_0 after 100 ps;
  I0_I_0 <= not I0;
  I2_I_0 <= not I2;
  I1_I_0 <= not I1;
  N_8 <= I3 or I2_I_0 or I1_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity IBUF is
port(
  O :  out std_logic;
  I :  in std_logic);
end IBUF;

architecture beh of IBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity IOBUF is
port(
  O :  out std_logic;
  IO :  inout std_logic;
  I :  in std_logic;
  T :  in std_logic);
end IOBUF;

architecture beh of IOBUF is
  signal UN0 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  UN0 <= not T;
  NN_1 <= '1';
  NN_2 <= '0';
  IO <= I after 100 ps when UN0 = '1' else 'Z' after 100 ps;
  O <= IO;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OBUF is
port(
  O :  out std_logic;
  I :  in std_logic);
end OBUF;

architecture beh of OBUF is
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  O <= I;
  NN_1 <= '1';
  NN_2 <= '0';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity OBUFT is
port(
  O :  out std_logic;
  I :  in std_logic;
  T :  in std_logic);
end OBUFT;

architecture beh of OBUFT is
  signal UN0 : std_logic ;
  signal NN_1 : std_logic ;
  signal NN_2 : std_logic ;
begin
  UN0 <= not T;
  NN_1 <= '1';
  NN_2 <= '0';
  O <= I after 100 ps when UN0 = '1' else 'Z' after 100 ps;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity BUFGP is
port(
  I :  in std_logic;
  O :  out std_logic);
end BUFGP;

architecture beh of BUFGP is
begin
  O <= I;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;

entity BUFG is
port(
  I :  in std_logic;
  O :  out std_logic);
end BUFG;