i2c_synplify.vhd

Xilinx ISE 官方源代码盘第十章

use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_BA is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_BA;

architecture beh of LUT3_BA is
  signal N_5 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_5 <= I2 and I1_I_0 after 100 ps;
  O <= N_5 or I0 after 100 ps;
  I1_I_0 <= not I1;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_C8 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_C8;

architecture beh of LUT3_C8 is
  signal N_4 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_4 <= I2 or I0 after 100 ps;
  O <= N_4 and I1 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_14 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_14;

architecture beh of LUT3_14 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
  signal N_12 : std_logic ;
  signal I0_I : std_logic ;
begin
  O <= N_12 and I0_I after 100 ps;
  GND <= '0';
  VCC <= '1';
  N_12 <= I2 xor I1 after 100 ps;
  I0_I <= not I0;
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_AAAB is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_AAAB;

architecture beh of LUT4_AAAB is
  signal N_8 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= N_8 or I0 after 100 ps;
  I3_I_0 <= not I3;
  I2_I_0 <= not I2;
  I1_I_0 <= not I1;
  N_8 <= I3_I_0 and I2_I_0 and I1_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_4000 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_4000;

architecture beh of LUT4_4000 is
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I0_I_0 <= not I0;
  O <= I3 and I2 and I1 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_A2AA is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_A2AA;

architecture beh of LUT4_A2AA is
  signal N_7 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= N_7 and I0 after 100 ps;
  I3_I_0 <= not I3;
  I1_I_0 <= not I1;
  N_7 <= I3_I_0 or I2 or I1_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_2220 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_2220;

architecture beh of LUT4_2220 is
  signal N_7 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_7 <= I3 or I2 after 100 ps;
  I1_I_0 <= not I1;
  O <= N_7 and I1_I_0 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_EEFE is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_EEFE;

architecture beh of LUT4_EEFE is
  signal N_7 : std_logic ;
  signal I3_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_7 <= I3_I_0 and I2 after 100 ps;
  I3_I_0 <= not I3;
  O <= N_7 or I1 or I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0800 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0800;

architecture beh of LUT4_0800 is
  signal I2_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I2_I_0 <= not I2;
  O <= I3 and I2_I_0 and I1 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_80 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_80;

architecture beh of LUT3_80 is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I2 and I1 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_1000 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_1000;

architecture beh of LUT4_1000 is
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  O <= I3 and I2 and I1_I_0 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_02 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_02;

architecture beh of LUT3_02 is
  signal I2_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I2_I_0 <= not I2;
  I1_I_0 <= not I1;
  O <= I2_I_0 and I1_I_0 and I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0100 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0100;

architecture beh of LUT4_0100 is
  signal I2_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I2_I_0 <= not I2;
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  O <= I3 and I2_I_0 and I1_I_0 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0010 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0010;

architecture beh of LUT4_0010 is
  signal I3_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I3_I_0 <= not I3;
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  O <= I3_I_0 and I2 and I1_I_0 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0040 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0040;

architecture beh of LUT4_0040 is
  signal I3_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I3_I_0 <= not I3;
  I0_I_0 <= not I0;
  O <= I3_I_0 and I2 and I1 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_04 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_04;

architecture beh of LUT3_04 is
  signal I2_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I2_I_0 <= not I2;
  I0_I_0 <= not I0;
  O <= I2_I_0 and I1 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT3_10 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  O :  out std_logic);
end LUT3_10;

architecture beh of LUT3_10 is
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  O <= I2 and I1_I_0 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_FFFE is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_FFFE;

architecture beh of LUT4_FFFE is
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  O <= I3 or I2 or I1 or I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_0004 is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_0004;

architecture beh of LUT4_0004 is
  signal I3_I_0 : std_logic ;
  signal I2_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I3_I_0 <= not I3;
  I2_I_0 <= not I2;
  I0_I_0 <= not I0;
  O <= I3_I_0 and I2_I_0 and I1 and I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_FF7F is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_FF7F;

architecture beh of LUT4_FF7F is
  signal I2_I_0 : std_logic ;
  signal I1_I_0 : std_logic ;
  signal I0_I_0 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  I2_I_0 <= not I2;
  I1_I_0 <= not I1;
  I0_I_0 <= not I0;
  O <= I3 or I2_I_0 or I1_I_0 or I0_I_0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library synplify;
use synplify.components.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;

entity LUT4_EEEA is
port(
  I0 :  in std_logic;
  I1 :  in std_logic;
  I2 :  in std_logic;
  I3 :  in std_logic;
  O :  out std_logic);
end LUT4_EEEA;

architecture beh of LUT4_EEEA is
  signal N_5 : std_logic ;
  signal N_6 : std_logic ;
  signal GND : std_logic ;
  signal VCC : std_logic ;
begin
  N_6 <= I3 or I2 after 100 ps;
  N_5 <= N_6 and I1 after 100 ps;
  O <= N_5 or I0 after 100 ps;
  GND <= '0';
  VCC <= '1';
end beh;

--